Einar J. Aas

34 papers A* 3A 2C 4Misc 1Journal 9Unranked 15
YearRankTypeTitle / Venue / Authors
2011 — conf
A programmable BIST with macro and micro codes for embedded SRAMs.
EWDTS
Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas, Mohammad Areef
2011 C conf
An Enhanced Path Delay Fault Simulator for Combinational Circuits.
DSD
Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas
2011 J jnl
Design of embedded TCAM based longest prefix match search engine.
Microprocess. Microsystems
Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas
2010 — conf
Experiments with ABIST test methodology applied to path delay fault testing.
EWDTS
Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas
2010 C conf
Path-Delay Fault Testing in Embedded Content Addressable Memories.
DSD
Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas
2009 — conf
Design of novel CAM core cell structures for an efficient implementation of low power BCAM system.
ACM Great Lakes Symposium on VLSI
Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas
2008 J jnl
Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications.
J. Signal Process. Syst.
Per Gunnar Kjeldsberg, Francky Catthoor, Sven Verdoolaege, Martin Palkovic, Arnout Vandecappelle, Qubo Hu, Einar J. Aas
2008 J jnl
Scan Test Response Compaction Combined with Diagnosis Capabilities.
J. Electron. Test.
Sverre Wichlund, Frank Berntsen, Einar J. Aas
2007 — conf
Probabilistic gate-level power estimation using a novel waveform set method.
ACM Great Lakes Symposium on VLSI
Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Einar J. Aas
2006 — conf
Reducing ATE Bandwidth and memory requirements: A diagnosis friendly scan test response compactor.
DFT
Sverre Wichlund, Frank Berntsen, Einar J. Aas
2006 — conf
Reducing Scan Test Data Volume and Time: A Diagnosis Friendly Finite Memory Compactor.
ATS
Sverre Wichlund, Einar J. Aas
2005 C conf
Remote Path Delay Fault Simulation.
DSD
Øystein Gjermundnes, Einar J. Aas
2004 J jnl
Storage requirement estimation for optimized design of data intensive applications.
ACM Trans. Design Autom. Electr. Syst.
Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas
2003 J jnl
Data dependency size estimation for use in memory optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas
2003 J jnl
On the Utilization of Java Technology in Embedded Systems.
Des. Autom. Embed. Syst.
Øyvind Strøm, Kjetil Svarstad, Einar J. Aas
2001 C conf
An Implementation of an Embedded Microprocessor Core with Support for Executing Byte Compiled Java Code.
DSD
Øyvind Strøm, Einar J. Aas
2001 A* conf
Detection of Partially Simultaneously Alive Signals in Storage Requirement Estimation for Data Intensive Applications.
DAC
Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas
2001 — conf
Formal verification of digital circuits by 3-valued simulation.
ICECS
Ayman M. Wahba, Einar J. Aas
2000 A conf
Automated Data Dependency Size Estimation with a Partially Fixed Execution Ordering.
ICCAD
Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas
2000 — conf
Design Quality and Design Efficiency; Definitions, Metrics and Relevant Design Experiences.
ISQED
Einar J. Aas
2000 — conf
On efficient CPU-usage in a VLSI CAD-environment with application to circuit partitioning.
ICECS
Sverre Wichlund, Einar J. Aas
2000 — conf
Storage requirement estimation for data intensive applications with partially fixed execution ordering.
CODES
Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas
1999 — conf
A Study of Dynamic Instruction Frequencies in Byte Compiled Java Programs.
EUROMICRO
Øyvind Strøm, Audun Klauseie, Einar J. Aas
1999 — conf
Project based learning objectives and experiences in electronic education: a memory controller design experiment.
ICECS
Einar J. Aas, Jukka Typpo
1996 — conf
4300 Megasamples/s Wave Digital Filter Implementation In Bit-parallel Tspc Circuit Technique.
ISSPA
Johnny Pihl, Einar J. Aas
1996 Misc conf
Comparison of two architectures for implementation of the discrete cosine transform.
ICASSP
Ingil Sundsbo, G. Lokken Hansen, Einar J. Aas
1994 J jnl
Quantifying Design Quality Through Design Experiments.
IEEE Des. Test Comput.
Einar J. Aas, Tore Steen, Karl Klingsheim
1993 — conf
Verification and Diagnosis of Digital Systems by Termary Reasoning.
CHARME
Ayman M. Wahba, Einar J. Aas
1991 J jnl
Combined probabilistic testability calculation and compact test generation for PLAs.
J. Electron. Test.
Bjørg Reppen, Einar J. Aas
1991 — conf
Experiments with autonomous test of PLAs.
EURO-DAC
Einar J. Aas, Gunnar Nystu
1990 A conf
State transition graph analysis as a key to BIST fault coverage.
ITC
Ove Brynestad, Einar J. Aas, Anne E. Vallestad
1984 J jnl
Test generation through logic programming.
Integr.
Dag Svanæs, Einar J. Aas
1978 A* conf
An integrated system for interactive editing of schematics, logic simulation and PCB layout design.
DAC
Hedayat Markus Bayegan, Einar J. Aas
1975 A* conf
Design automation in norway.
DAC
P. A. Arneberg, Einar J. Aas