Eero Aho

18 papers A 1C 2Journal 8Unranked 6
YearRankTypeTitle / Venue / Authors
2012 — conf
Towards real-time applications in mobile web browsers.
ESTIMedia
Eero Aho, Kimmo Kuusilinna, Tomi Aarnio, Janne Pietiainen, Jari Nikara
2011 — conf
OpenCL implementation of Cholesky matrix decomposition.
SoC
Claudio Brunelli, Eero Aho, Heikki Berg
2009 J jnl
A Configurable Motion Estimation Architecture for Block-Matching Algorithms.
IEEE Trans. Circuits Syst. Video Technol.
Jarno Vanne, Eero Aho, Kimmo Kuusilinna, Timo D. Hämäläinen
2009 A conf
A case for multi-channel memories in video recording.
DATE
Eero Aho, Jari Nikara, Petri A. Tuominen, Kimmo Kuusilinna
2009 — conf
Memory access characteristics of H.264 video encoder on embedded processor.
SiPS
Eero Aho, Kimmo Kuusilinna, Jari Nikara
2009 — conf
Performance analysis of multi-channel memories in mobile devices.
SoC
Jari Nikara, Eero Aho, Petri A. Tuominen, Kimmo Kuusilinna
2008 J jnl
A Parallel Memory System for Variable Block-Size Motion Estimation Algorithms.
IEEE Trans. Circuits Syst. Video Technol.
Jarno Vanne, Eero Aho, Timo D. Hämäläinen, Kimmo Kuusilinna
2008 J jnl
Configurable Data Memory for Multimedia Processing.
J. Signal Process. Syst.
Eero Aho, Jarno Vanne, Timo D. Hämäläinen
2007 J jnl
Configurable implementation of parallel memory based real-time video downscaler.
Microprocess. Microsystems
Eero Aho, Jarno Vanne, Timo D. Hämäläinen, Kimmo Kuusilinna
2006 J jnl
A High-Performance Sum of Absolute Difference Implementation for Motion Estimation.
IEEE Trans. Circuits Syst. Video Technol.
Jarno Vanne, Eero Aho, Timo Hämäläinen, Kimmo Kuusilinna
2006 — —
Design and implementation of parallel memory architectures.
Eero Aho
2006 C conf
Parallel Memory Architecture for Arbitrary Stride Accesses.
DDECS
Eero Aho, Jarno Vanne, Timo D. Hämäläinen
2006 — conf
Parallel Memory Implementation for Arbitrary Stride Accesses.
ICSAMOS
Eero Aho, Jarno Vanne, Timo D. Hämäläinen
2005 — conf
Block-level parallel processing for scaling evenly divisible frames.
ISCAS (2)
Eero Aho, Jarno Vanne, Kimmo Kuusilinna, Timo Hämäläinen
2005 J jnl
Block-level parallel processing for scaling evenly divisible images.
IEEE Trans. Circuits Syst. I Regul. Pap.
Eero Aho, Jarno Vanne, Timo D. Hämäläinen, Kimmo Kuusilinna
2005 J jnl
Comments on "Winscale: an image-scaling algorithm using an area pixel Model".
IEEE Trans. Circuits Syst. Video Technol.
Eero Aho, Jarno Vanne, Kimmo Kuusilinna, Timo D. Hämäläinen
2004 J jnl
Address Computation in Configurable Parallel Memory Architecture.
IEICE Trans. Inf. Syst.
Eero Aho, Jarno Vanne, Kimmo Kuusilinna, Timo D. Hämäläinen
2002 C conf
Enhanced Configurable Parallel Memory Architecture.
DSD
Jarno Vanne, Eero Aho, Kimmo Kuusilinna, Timo D. Hämäläinen