Edward S. Davidson

100 papers A* 26A 15B 6C 6Misc 1Journal 29Unranked 16

Year	Rank	Type	Title / Venue / Authors
2014	—	`conf`	Author retrospective for optimum modulo schedules for minimum register requirements. ICS 25th Anniversary Alexandre E. Eichenberger, Edward S. Davidson, Santosh G. Abraham
2008	A	`conf`	A freespace crossbar for multi-core processors. ICS Michel N. Victor, Aris K. Silzars, Edward S. Davidson
2004	J	`jnl`	A Prefetch Taxonomy. IEEE Trans. Computers Viji Srinivasan, Edward S. Davidson, Gary S. Tyson
2004	A	`conf`	Probabilistic Predicate-Aware Modulo Scheduling. CGO Mikhail Smelyanskiy, Scott A. Mahlke, Edward S. Davidson
2003	J	`jnl`	Call graph prefetching for database applications. ACM Trans. Comput. Syst. Murali Annavaram, Jignesh M. Patel, Edward S. Davidson
2003	A	`conf`	Predicate-Aware Scheduling: A Technique for Reducing Resource Constraints. CGO Mikhail Smelyanskiy, Scott A. Mahlke, Edward S. Davidson, Hsien-Hsin S. Lee
2002	A	`conf`	Boosting trace cache performance with nonhead miss speculation. ICS Stevan A. Vlaovic, Edward S. Davidson
2002	C	`conf`	TAXI: Trace Analysis for X86 Interpretation. ICCD Stevan A. Vlaovic, Edward S. Davidson
2001	C	`conf`	Allocation by Conflict: A Simple Effective Multilateral Cache Management Scheme. ICCD Edward S. Tam, Stevan A. Vlaovic, Gary S. Tyson, Edward S. Davidson
2001	A*	`conf`	Branch History Guided Instruction Prefetching. HPCA Viji Srinivasan, Edward S. Davidson, Gary S. Tyson, Mark J. Charney, Thomas R. Puzak
2001	A*	`conf`	Call Graph Prefetching for Database Applications. HPCA Murali Annavaram, Jignesh M. Patel, Edward S. Davidson
2001	A*	`conf`	Data prefetching by dependence graph precomputation. ISCA Murali Annavaram, Jignesh M. Patel, Edward S. Davidson
2001	J	`jnl`	Evaluating the Use of Register Queues in Software Pipelined Loops. IEEE Trans. Computers Gary S. Tyson, Mikhail Smelyanskiy, Edward S. Davidson
2000	A*	`conf`	Improving BTB performance in the presence of DLLs. MICRO Stevan A. Vlaovic, Edward S. Davidson, Gary S. Tyson
2000	B	`conf`	Instruction overhead and data locality effects in superscalar processors. ISPASS Murali Annavaram, Gary S. Tyson, Edward S. Davidson
2000	—	`conf`	Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining. IEEE PACT Mikhail Smelyanskiy, Gary S. Tyson, Edward S. Davidson
1999	J	`jnl`	Active Management of Data Caches by Exploiting Reuse Information. IEEE Trans. Computers Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson
1999	A*	`conf`	Dual-Issue Scheduling with Spills for Binary Trees. SODA Waleed Meleis, Edward S. Davidson
1999	J	`jnl`	Introduction to "The ENIAC". Proc. IEEE Arthur W. Burks, Edward S. Davidson
1998	J	`jnl`	Characterizing Distributed Shared Memory Performance: A Case Study of the Convex SPP1000. IEEE Trans. Parallel Distributed Syst. Gheith A. Abandah, Edward S. Davidson
1998	—	`conf`	Configuration Independent Analysis for Characterizing Shared-Memory Applications. IPPS/SPDP Gheith A. Abandah, Edward S. Davidson
1998	A*	`conf`	Effects of Architectural and Technological Advances on the HP/Convex Exemplar's Memory and Communication Performance. ISCA Gheith A. Abandah, Edward S. Davidson
1998	C	`conf`	Evaluating the performance of active cache management schemes. ICCD Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson
1998	—	`conf`	Improving the Throughput of a Pipeline by Insertion of Delays. 25 Years ISCA: Retrospectives and Reprints Janak H. Patel, Edward S. Davidson
1998	—	`conf`	Origin 2000 Design Enhancements for Communication Intensive Applications. IEEE PACT Gheith A. Abandah, Edward S. Davidson
1998	—	`conf`	Retrospective: The Cedar System. 25 Years ISCA: Retrospectives and Reprints Alexander V. Veidenbaum, Pen-Chung Yew, David J. Kuck, Constantine D. Polychronopoulos, David A. Padua, Edward S. Davidson, Kyle A. Gallivan
1998	—	`conf`	The Cedar System and an Initial Performance Study. 25 Years ISCA: Retrospectives and Reprints David J. Kuck, Edward S. Davidson, Duncan H. Lawrie, Ahmed H. Sameh, Chuan-Qi Zhu
1998	A	`conf`	Utilizing Reuse Information in Data Cache Management. International Conference on Supercomputing Jude A. Rivers, Edward S. Tam, Gary S. Tyson, Edward S. Davidson, Matthew K. Farrens
1998	B	`conf`	mlcache: A Flexible Multi-Lateral Cache Simulator. MASCOTS Edward S. Tam, Jude A. Rivers, Gary S. Tyson, Edward S. Davidson
1997	A*	`conf`	Efficient Formulation for Optimal Modulo Schedulers. PLDI Alexandre E. Eichenberger, Edward S. Davidson
1997	C	`conf`	On Effective Data Supply For Multi-Issue Processors. ICCD Jude A. Rivers, Edward S. Tam, Edward S. Davidson
1997	A*	`conf`	On High-Bandwidth Data Cache Design for Multi-Issue Processors. MICRO Jude A. Rivers, Gary S. Tyson, Edward S. Davidson, Todd M. Austin
1996	A*	`conf`	A Reduced Multipipeline Machine Description that Preserves Scheduling Constraints. PLDI Alexandre E. Eichenberger, Edward S. Davidson
1996	J	`jnl`	Minimizing Register Requirements of a Modulo Schedule via Optimum Stage Scheduling. Int. J. Parallel Program. Alexandre E. Eichenberger, Edward S. Davidson, Santosh G. Abraham
1996	—	`conf`	Modeling the Communication Performance of the IBM SP2. IPPS Gheith A. Abandah, Edward S. Davidson
1996	J	`jnl`	Performance Issues in Integrating Temporality-Based Caching with Prefetching. Perform. Evaluation Jude A. Rivers, Edward S. Davidson
1996	A	`conf`	Profile Driven Weighted Decomposition. International Conference on Supercomputing Karen A. Tomko, Edward S. Davidson
1996	—	`conf`	Reducing Conflicts in Direct-Mapped Caches with a Temporality-Based Design. ICPP, Vol. 1 Jude A. Rivers, Edward S. Davidson
1995	J	`jnl`	Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability, and startability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah
1995	A	`conf`	Optimum Modulo Schedules for Minimum Register Requirements. International Conference on Supercomputing Alexandre E. Eichenberger, Edward S. Davidson, Santosh G. Abraham
1995	A*	`conf`	Register allocation for predicated code. MICRO Alexandre E. Eichenberger, Edward S. Davidson
1995	A*	`conf`	Stage scheduling: a technique to reduce the register requirements of a modulo schedule. MICRO Alexandre E. Eichenberger, Edward S. Davidson
1995	C	`conf`	The resource conflict methodology for early-stage design space exploration of superscalar RISC processors. ICCD John-David Wellman, Edward S. Davidson
1994	—	`conf`	A Hierarchical Approach to Modeling and Improving the Performance of Scientific Applications on the KSR1. ICPP (3) Eric L. Boyd, Waqar Azeem, Hsien-Hsin S. Lee, Tien-Pao Shih, Shih-Hao Hung, Edward S. Davidson
1994	A	`conf`	Communication in the KSR1 MPP: performance evaluation using synthetic workload experiments. International Conference on Supercomputing Eric L. Boyd, Edward S. Davidson
1994	B	`conf`	Grouping Array Layouts to Reduce Communication and Improve Locality of Parallel Programs. ICPADS Tien-Pao Shih, Edward S. Davidson
1994	A*	`conf`	Minimum register requirements for a modulo schedule. MICRO Alexandre E. Eichenberger, Edward S. Davidson, Santosh G. Abraham
1994	A	`conf`	Optimal local register allocation for a multiple-issue machine. International Conference on Supercomputing Waleed Meleis, Edward S. Davidson
1993	J	`jnl`	Approaching a machine-application bound in delivered performance on scientific code. Proc. IEEE William H. Mangione-Smith, Tien-Pao Shih, Santosh G. Abraham, Edward S. Davidson
1993	A	`conf`	Evaluating the Communication Performance of MPPs Using Synthetic Sparse Matrix Multiplication Workloads. International Conference on Supercomputing Eric L. Boyd, John-David Wellman, Santosh G. Abraham, Edward S. Davidson
1993	A*	`conf`	Hierarchical Performance Modeling with MACS: A Case Study of the Convex C-240. ISCA Eric L. Boyd, Edward S. Davidson
1993	—	`conf`	KSR 1 Multiprocessor: Analysis of Latency Hiding Techniques in a Sparse Solver. IPPS Daniel Windheiser, Eric L. Boyd, Eric Hao, Santosh G. Abraham, Edward S. Davidson
1993	J	`jnl`	Synchronization of pipelines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Karem A. Sakallah, Trevor N. Mudge, Timothy M. Burks, Edward S. Davidson
1993	A*	`conf`	The Cedar System and an Initial Performance Study. ISCA David J. Kuck, Edward S. Davidson, Duncan H. Lawrie, Ahmed H. Sameh, Chuan-Qi Zhu, Alexander V. Veidenbaum, Jeff Konicek, Pen-Chung Yew, Kyle A. Gallivan, William Jalby, Harry A. G. Wijshoff, Randall Bramley, Ulrike Meier Yang, Perry A. Emrath, David A. Padua, Rudolf Eigenmann, Jay P. Hoeflinger, Greg P. Jaxon, Zhiyuan Li, T. Murphy, John T. Andrews, Stephen W. Turner
1992	A	`conf`	Register requirements of pipelined processors. ICS William H. Mangione-Smith, Santosh G. Abraham, Edward S. Davidson
1992	A	`conf`	Using constraint geometry to determine maximum rate pipeline clocking. ICCAD Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah
1991	J	`jnl`	A Performance Comparison of the IBM RS/6000 and the Astronautics ZS-1. Computer William H. Mangione-Smith, Santosh G. Abraham, Edward S. Davidson
1991	A*	`conf`	An integrated approach to developing manufacturing control software. ICRA Jarir K. Chaar, Richard A. Volz, Edward S. Davidson
1991	C	`conf`	Optimal Clocking of Circular Pipelines. ICCD Karem A. Sakallah, Trevor N. Mudge, Timothy M. Burks, Edward S. Davidson
1991	A	`ed.`	Proceedings of the 5th international conference on Supercomputing, ICS 1991, Cologne, Germany, June 17-21, 1991 ICS Edward S. Davidson, Friedel Hossfeld
1991	—	`conf`	The Organization of the Cedar System. ICPP (1) Jeff Konicek, Tracy Tilton, Alexander V. Veidenbaum, Chuan-Qi Zhu, Edward S. Davidson, Ruppert A. Downing, Michael J. Haney, Manish Sharma, Pen-Chung Yew, P. Michael Farmwald, David J. Kuck, Daniel M. Lavery, Robert A. Lindsey, D. Pointer, John T. Andrews, Thomas Beck, T. Murphy, Stephen W. Turner, Nancy J. Warter
1991	A*	`conf`	Vector Register Design for Polycyclic Vector Scheduling. ASPLOS William H. Mangione-Smith, Santosh G. Abraham, Edward S. Davidson
1990	A*	`conf`	Cyclic job shop scheduling using reservation tables. ICRA Jarir K. Chaar, Edward S. Davidson
1988	A	`conf`	An evaluation of Cray X-MP performance on vectorizable Livermore FORTRAN kernels. ICS J. H. Tang, Edward S. Davidson
1988	A*	`conf`	Analysis of Memory Referencing Behavior For Design of Local Memories. ISCA Geoffrey D. McNiven, Edward S. Davidson
1988	J	`jnl`	Pairwise Reduction for the Direct, Parallel Solution of Sparse, Unsymmetric Sets of Linear Equations. IEEE Trans. Computers Timothy A. Davis, Edward S. Davidson
1988	A	`conf`	Polycyclic Vector scheduling vs. Chaining on 1-Port Vector supercomputers. SC J. H. Tang, Edward S. Davidson, J. Tong
1987	J	`jnl`	Characterization of Branch and Data Dependencies in Programs for Evaluating Pipeline Performance. IEEE Trans. Computers Philip G. Emma, Edward S. Davidson
1987	B	`conf`	PSOLVE : A Concurrent Algorithm for Solving Sparse Systems of Linear Equations. ICPP Timothy A. Davis, Edward S. Davidson
1986	—	`conf`	A Broader Range of Possible Answers to the Issues Raised by RISC. COMPCON Edward S. Davidson
1986	B	`conf`	A Communication Model for Optimizing Hierarchical Multiprocessor Systems. ICPP Santosh G. Abraham, Edward S. Davidson
1986	—	`conf`	Features of the Structured Memory Access (SMA) Architecture. COMPCON Andrew R. Pleszkun, Gurindar S. Sohi, Bassam Z. Kahhaleh, Edward S. Davidson
1986	A*	`conf`	Highly Concurrent Scalar Processing. ISCA Peter Y.-T. Hsu, Edward S. Davidson
1985	Misc	`conf`	A custom-designed integrated circuit for the realization of residue number digital filters. ICASSP W. K. Jenkins, Edward S. Davidson, D. F. Paul
1985	A*	`conf`	An Efficient LISP-Execution Architecture with a New Representation for List Structures. ISCA Gurindar S. Sohi, Edward S. Davidson, Janak H. Patel
1985	A*	`conf`	TIDBITS: Speedup Via Time-Delay Bit-Slicing in ALU Design for VLSI Technology. ISCA Peter Y.-T. Hsu, Joseph T. Rahmeh, Edward S. Davidson, Jacob A. Abraham
1984	A*	`conf`	Design of Instruction Set Architectures for Support of High-Level Languages . ISCA Pradip Bose, Edward S. Davidson
1983	A*	`conf`	Performance of Shared Cache for Parallel-Pipelined Computer Systems ISCA Phil C. C. Yeh, Janak H. Patel, Edward S. Davidson
1983	J	`jnl`	Shared Cache for Multiple-Stream Computer Systems. IEEE Trans. Computers Phil C. C. Yeh, Janak H. Patel, Edward S. Davidson
1983	B	`conf`	Structured Memory Access Architecture. ICPP Andrew R. Pleszkun, Edward S. Davidson
1982	—	`conf`	Evaluating database management systems. AFIPS National Computer Conference Edward S. Davidson
1982	J	`jnl`	Memory Interference in Synchronous Multiprocessor Systems. IEEE Trans. Computers David W. L. Yen, Janak H. Patel, Edward S. Davidson
1981	J	`jnl`	A Comparison of Dynamic and Static Virtual Memory Allocation Algorithms. IEEE Trans. Software Eng. Robert L. Budzinski, Edward S. Davidson
1981	J	`jnl`	DMIN: An Algorithm for Computing the Optimal Dynamic Allocation in a Virtual Memory Computer. IEEE Trans. Software Eng. Robert L. Budzinski, Edward S. Davidson, Wataru Mayeda, Harold S. Stone
1980	A*	`conf`	A Multiple Stream Microprocessor Prototype System: AMP-1. ISCA Edward S. Davidson
1980	J	`jnl`	Computer System Design Using a Hierarchical Approach to Performance Evaluation. Commun. ACM B. Kumar, Edward S. Davidson
1979	J	`jnl`	Special Feature: Developing a Multiple-Instruction-Stream Single-Chip Processor. Computer William Joseph Kaminsky Jr., Edward S. Davidson
1978	J	`jnl`	Performance Evaluation of Highly Concurrent Computers by Deterministic Simulation. Commun. ACM B. Kumar, Edward S. Davidson
1977	A*	`conf`	Information Content of CPU Memory Referencing Behavior. ISCA Dan W. Hammerstrom, Edward S. Davidson
1977	J	`jnl`	Organization of Semiconductor Memories for Parallel-Pipelined Processors. IEEE Trans. Computers Faye A. Briggs, Edward S. Davidson
1976	A*	`conf`	Improving the Throughput of a Pipeline by Insertion of Delays. ISCA Janak H. Patel, Edward S. Davidson
1974	J	`jnl`	A multiminiprocessor system implemented through pipelining. Computer Leonard E. Shar, Edward S. Davidson
1974	—	`conf`	Optimal Searching Algorithms for Parallel Pipelined Computers. Sagamore Computer Conference Daniel L. Weller, Edward S. Davidson
1974	J	`jnl`	Redundancy Testing in Combinational Networks. IEEE Trans. Computers Hsien-Hsin S. Lee, Edward S. Davidson
1972	J	`jnl`	A Transform for NAND Network Design. IEEE Trans. Computers Hsiao-Peng Lee, Edward S. Davidson
1972	J	`jnl`	Comments on "A Minimization Technique for TANT Networks". IEEE Trans. Computers Hsiao-Peng Lee, Edward S. Davidson
1969	J	`jnl`	An Algorithm for NAND Decomposition Under Network Constraints. IEEE Trans. Computers Edward S. Davidson
1969	J	`jnl`	Authors' Reply IEEE Trans. Computers Edward S. Davidson, Gernot Metze
1968	—	`—`	An Algorithm for Nand Decomposition of Combinational Switching Functions Edward S. Davidson
1968	J	`jnl`	Comments on "An Algorithm for Synthesis of Multiple-Output Combinational Logic". IEEE Trans. Computers Edward S. Davidson, Gernot Metze