Edward A. Stott

21 papers A* 1A 5B 6Misc 3Journal 4Unranked 2
YearRankTypeTitle / Venue / Authors
2018 J jnl
KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs.
ACM Trans. Reconfigurable Technol. Syst.
James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides
2018 — conf
KOCL: Kernel-level Power Estimation for Arbitrary FPGA-SoC-accelerated OpenCL Applications.
IWOCL
James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides
2017 J jnl
KOCL: Power Self- Awareness for Arbitrary FPGA-SoC-Accelerated OpenCL Applications.
IEEE Des. Test
James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides
2017 B conf
STRIPE: Signal selection for runtime power estimation.
FPL
James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides
2016 Misc conf
KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs.
FCCM
Eddie Hung, James J. Davis, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides
2016 A conf
Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only).
FPGA
James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides
2015 — conf
Adaptive energy minimization of embedded heterogeneous systems using regression-based learning.
PATMOS
Sheng Yang, Rishad A. Shafik, Geoff V. Merrett, Edward A. Stott, Joshua M. Levine, James J. Davis, Bashir M. Al-Hashimi
2015 A conf
Delay-Bounded Routing for Shadow Registers.
FPGA
Eddie Hung, Joshua M. Levine, Edward A. Stott, George A. Constantinides, Wayne Luk
2014 A* conf
Datapath Synthesis for Overclocking: Online Arithmetic for Latency-Accuracy Trade-offs.
DAC
Kan Shi, David Boland, Edward A. Stott, Samuel Bayliss, George A. Constantinides
2014 A conf
Dynamic voltage & frequency scaling with online slack measurement.
FPGA
Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung
2014 Misc conf
Timing Fault Detection in FPGA-Based Circuits.
FCCM
Edward A. Stott, Joshua M. Levine, Peter Y. K. Cheung, Nachiket Kapre
2013 B conf
SMI: Slack Measurement Insertion for online timing monitoring in FPGAs.
FPL
Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung
2013 J jnl
Variation and Reliability in FPGAs.
IEEE Des. Test
Edward A. Stott, Zhenyu Guan, Joshua M. Levine, Justin S. J. Wong, Peter Y. K. Cheung
2012 Misc conf
Online Measurement of Timing in Circuits: For Health Monitoring and Dynamic Voltage & Frequency Scaling.
FCCM
Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung
2011 A conf
Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only).
FPGA
Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung
2011 B conf
Improving FPGA Reliability with Wear-Levelling.
FPL
Edward A. Stott, Peter Y. K. Cheung
2010 B conf
Degradation Analysis and Mitigation in FPGAs.
FPL
Edward A. Stott, Justin S. J. Wong, Peter Y. K. Cheung
2010 A conf
Degradation in FPGAs: measurement and modelling.
FPGA
Edward A. Stott, Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung
2010 J jnl
Fault tolerance and reliability in field-programmable gate arrays.
IET Comput. Digit. Tech.
Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung
2009 B conf
Compensating for variability in FPGAs by re-mapping and re-placement.
FPL
N. Pete Sedcole, Edward A. Stott, Peter Y. K. Cheung
2008 B conf
Fault tolerant methods for reliability in FPGAs.
FPL
Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung