Eduardo J. Peralías

67 papers A* 1A 8B 3C 9Misc 2Journal 16Unranked 28

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	An Automation-Oriented Approach for RF/mm-Wave Multi-Stage LNA. PRIME Roberto Méndez-Romero, Eduardo J. Peralías, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, Rafaella Fiorelli
2025	—	`conf`	Design-Oriented Active Balun for $6-\text{GHz}$ and Low-Voltage Applications. NewCAS Roberto Méndez-Romero, Eduardo J. Peralías, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, Rafaella Fiorelli
2025	C	`conf`	On the Validity of SEE Simulation for Rad-Hard Analog ASICs. IOLTS Valentin Gutierrez, Carlos M. Domínguez-Matas, Gildas Léger, Antonio J. Ginés, Eduardo J. Peralías
2023	B	`conf`	A Single-Event Latchup setup for high-precision AMS circuits. ETS Gildas Léger, Antonio J. Ginés, Eduardo J. Peralías, Valentin Gutierrez, Carlos M. Domínguez-Matas, Maria Angeles Jalón, L. Carranza
2023	J	`jnl`	Behavioral Model for High-Speed SAR ADCs With On-Chip References. IEEE Trans. Very Large Scale Integr. Syst. Carlos Manuel Domínguez-Matas, Antonio J. Ginés, Aránzazu Otín, Valentin Gutierrez, Gildas Léger, Eduardo J. Peralías
2021	J	`jnl`	Digital Non-Linearity Calibration for ADCs With Redundancy Using a New LUT Approach. IEEE Trans. Circuits Syst. I Regul. Pap. Antonio J. Ginés, Gildas Léger, Eduardo J. Peralías
2020	C	`conf`	Calibration of Capacitor Mismatch and Static Comparator Offset in SAR ADC with Digital Redundancy. ISCAS Antonio Lopez-Angulo, Antonio J. Ginés, Eduardo J. Peralías
2020	—	`conf`	Digital calibration of capacitor mismatch and comparison offset in Split-CDAC SAR ADCs with redundancy. NEWCAS Antonio Lopez-Angulo, Antonio J. Ginés, Eduardo J. Peralías
2020	C	`conf`	Fast Simulation of Non-Linear Circuits using Semi-Analytical Solutions Based on the Matrix Exponential. ISCAS J. A. Serrano, Antonio J. Ginés, Eduardo J. Peralías
2020	—	`conf`	Non-Linear Calibration of Pipeline ADCs using a Histogram-Based Estimation of the Redundant INL. NEWCAS Antonio J. Ginés, Gildas Léger, Eduardo J. Peralías
2020	J	`jnl`	Normalized Nonlinear Semiempirical MOST Model Used in Monolithic RF Class A-to-C PAs. Circuits Syst. Signal Process. Rafaella Fiorelli, Nicolás Barabino, Fernando Silveira, Eduardo J. Peralías
2019	—	`conf`	Mismatch and Offset Calibration in Redundant SAR ADC. DCIS Antonio Lopez-Angulo, Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
2018	C	`conf`	Description of SAR ADCs with Digital Redundancy using a Unified Hardware-Based Approach. ISCAS Antonio J. Ginés, Antonio Lopez-Angulo, Eduardo J. Peralías, Adoración Rueda
2018	—	`conf`	Redundant SAR ADCs with Split-capacitor DAC. ICECS Antonio Lopez-Angulo, Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
2017	J	`jnl`	Black-Box Calibration for ADCs With Hard Nonlinear Errors Using a Novel INL-Based Additive Code: A Pipeline ADC Case Study. IEEE Trans. Circuits Syst. I Regul. Pap. Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
2017	J	`jnl`	Fast Background Calibration of Sampling Timing Skew in SHA-Less Pipeline ADCs. IEEE Trans. Very Large Scale Integr. Syst. Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
2017	A	`conf`	On the limits of machine learning-based test: A calibrated mixed-signal system case study. DATE Manuel J. Barragán, Gildas Léger, Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
2016	B	`conf`	Linearity test of high-speed high-performance ADCs using a self-testable on-chip generator. ETS Antonio J. Ginés, Eduardo J. Peralías, Gildas Léger, Adoración Rueda, Guillaume Renaud, Manuel J. Barragán, Salvador Mir
2016	J	`jnl`	Semi-empirical RF MOST model for CMOS 65 nm technologies: Theory, extraction method and validation. Integr. Rafaella Fiorelli, Eduardo J. Peralías
2015	—	`conf`	An approach to the design of low-jitter differential clock recovery circuits for high performance ADCs. LASCAS Juan Núñez, Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
2015	J	`jnl`	Background Digital Calibration of Comparator Offsets in Pipeline ADCs. IEEE Trans. Very Large Scale Integr. Syst. Antonio Jose Ginés, Eduardo J. Peralías, Adoración Rueda
2014	—	`conf`	Closed-loop simulation method for evaluation of static offset in discrete-time comparators. ICECS Antonio J. Ginés, Eduardo J. Peralías, Gildas Léger, Adoración Rueda
2014	B	`conf`	INL systematic reduced-test technique for Pipeline ADCs. ETS Eduardo J. Peralías, Antonio Jose Ginés, Adoración Rueda
2012	C	`conf`	Analysis of steady-state common-mode response in differential LC-VCOs. ISCAS Ricardo Doldán, Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
2012	—	`conf`	Self-biased input common-mode generation for improving dynamic range and yield in inverter-based filters. ICECS Antonio Jose Ginés, Alberto Villegas, Eduardo J. Peralías, Adoración Rueda
2011	—	`conf`	2.4-GHz single-ended input low-power low-voltage active front-end for ZigBee applications in 90 nm CMOS. ECCTD Rafaella Fiorelli, Alberto Villegas, Eduardo J. Peralías, Diego Vázquez, Adoración Rueda
2011	—	`conf`	A 3.6mW @ 1.2V high linear 8 ESSCIRC Alberto Villegas, Diego Vázquez, Eduardo J. Peralías, Adoración Rueda
2011	J	`jnl`	Blind Adaptive Estimation of Integral Nonlinear Errors in ADCs Using Arbitrary Input Stimulus. IEEE Trans. Instrum. Meas. Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
2010	—	`conf`	A fully differential monolithic 2.4GHZ PA for IEEE 802.15.4 based on efficiency design flow. ICECS Rafaella Fiorelli, Eduardo J. Peralías, Nicolás Barabino, Fernando Silveira
2010	J	`jnl`	ADC Non-Linearity Low-Cost Test Through a Simplified Double-Histogram Method. J. Electron. Test. Maria Angeles Jalón, Eduardo J. Peralías
2010	J	`jnl`	On Chopper Effects in Discrete-Time SigmaDelta Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. Gildas Léger, Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
2010	C	`conf`	On-chip biased voltage-controlled oscillator with temperature compensation of the oscillation amplitude for robust I/Q generation. ISCAS Antonio J. Ginés, Ricardo Doldán, Manuel J. Barragan Asian, Adoración Rueda, Eduardo J. Peralías
2010	—	`conf`	Power optimization of CMOS programmable gain amplifiers with high dynamic range and common-mode feed-forward circuit. ICECS Antonio J. Ginés, Ricardo Doldán, Adoración Rueda, Eduardo J. Peralías
2009	—	`conf`	A survey on digital background calibration of ADCs. ECCTD Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
2009	—	`conf`	On-line estimation of the integral non-linear errors in analogue-to-digital converters without histogram evaluation. ECCTD Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
2009	—	`conf`	Phase noise - consumption trade-off in low power RF-LC-VCO design in micro and nanometric technologies. SBCCI Rafaella Fiorelli, Fernando Silveira, Eduardo J. Peralías
2008	—	`conf`	A 1.2V 5.14mW quadrature frequency synthesizer in 90nm CMOS technology for 2.4GHz ZigBee applications. APCCAS Antonio Jose Ginés, Ricardo Doldán, Alberto Villegas, Antonio J. Acosta, Maria Angeles Jalón, Diego Vázquez, Adoración Rueda, Eduardo J. Peralías
2008	—	`conf`	A 2.4GHz LNA in a 90-nm CMOS technology designed with ACM model. SBCCI Rafaella Fiorelli, Fernando Silveira, Eduardo J. Peralías, Diego Vázquez, Adoración Rueda, José Luis Huertas
2008	—	`conf`	A 5GHz wide tuning range LC-VCO in sub-micrometer CMOS technology. APCCAS Ricardo Doldán Lorenzo, Antonio Jose Ginés Arteaga, Adoración Rueda, Eduardo J. Peralías
2008	J	`jnl`	Simple Evaluation of the Nonlinearity Signature of an ADC Using a Spectral Approach. VLSI Design Eduardo J. Peralías, Maria Angeles Jalón, Adoración Rueda
2007	C	`conf`	Improved Background Algorithms for Pipeline ADC Full Calibration. ISCAS Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
2007	—	`conf`	Novel swapping technique for background calibration of capacitor mismatching in pipeline ADCS. SBCCI Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
2006	C	`conf`	Statistical analysis of a background correlation-based technique for full calibration of pipeline ADCs. ISCAS Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
2005	—	`conf`	Digital self-tuning technique for continuous-time filters. ICECS Guillermo Zatorre-Navarro, Eduardo J. Peralías, Santiago Celma Pueyo, Concepción Aldea Chagoyen, Nicolás J. Medrano-Marqués
2005	—	`conf`	Full calibration digital techniques for pipeline ADCs. ISCAS (3) Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
2004	A	`conf`	Digital Background Gain Error Correction in Pipeline ADCs. DATE Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
2004	J	`jnl`	Impact of random channel mismatch on the SNR and SFDR of time-interleaved ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. Gildas Léger, Eduardo J. Peralías, Adoración Rueda, José Luis Huertas
2003	—	`conf`	Digital Background Calibration Technique for Pipeline ADCs with Multi-Bit Stages. SBCCI Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
2002	A	`conf`	A Mixed-Signal Design Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal Effects. DATE Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda, Ralf Seepold, Natividad Martínez Madrid
2002	J	`jnl`	Practical Oscillation-Based Test of Integrated Filters. IEEE Des. Test Comput. Gloria Huertas, Diego Vázquez, Eduardo J. Peralías, Adoración Rueda, José Luis Huertas
2002	J	`jnl`	Testing Mixed-Signal Cores: A Practical Oscillation-Based Test in an Analog Macrocell. IEEE Des. Test Comput. Gloria Huertas, Diego Vázquez, Eduardo J. Peralías, Adoración Rueda, José Luis Huertas
2001	A	`conf`	Analog/mixed-signal IP modeling for design reuse. DATE Natividad Martínez Madrid, Eduardo J. Peralías, Antonio J. Acosta, Adoración Rueda
2001	J	`jnl`	New BIST Schemes for Structural Testing of Pipelined Analog to Digital Converters. J. Electron. Test. Eduardo J. Peralías, Adoración Rueda, José Luis Huertas
2001	Misc	`conf`	Self-Testable Pipelined ADC with Low Hardware Overhead. VTS Eduardo J. Peralías, Gloria Huertas, Adoración Rueda, José L. Huertas
2001	—	`conf`	Structural testing of pipelined analog to digital converters. ISCAS (1) Eduardo J. Peralías, Adoración Rueda, José L. Huertas
2000	A	`conf`	A Vhdl-Based Methodology for Design and Verification of Pipeline A/D Converters. DATE Eduardo J. Peralías, Antonio J. Acosta, Adoración Rueda, José L. Huertas
2000	—	`conf`	Alternative DFT Strategies for High-Speed Pipelined Data Converters. LATW Eduardo J. Peralías, Adoración Rueda, José L. Huertas
2000	—	`conf`	An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits. PATMOS Raúl Jiménez, Antonio J. Acosta, Eduardo J. Peralías, Adoración Rueda
2000	—	`conf`	Testing mixed-signal cores: practical oscillation-based test in an analog macrocell. Asian Test Symposium Gloria Huertas, Diego Vázquez, Eduardo J. Peralías, Adoración Rueda, José L. Huertas
2000	C	`conf`	VHDL-based behavioural description of pipeline ADCs. ISCAS Eduardo J. Peralías, Antonio J. Acosta, Adoración Rueda, José L. Huertas
1998	J	`jnl`	A high-Q bandpass fully differential SC filter with enhanced testability. IEEE J. Solid State Circuits Diego Vázquez, Adoración Rueda, José Luis Huertas, Eduardo J. Peralías
1998	A	`conf`	An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits. DATE Juan A. Prieto, Adoración Rueda, Ian Andrew Grout, Eduardo J. Peralías, José L. Huertas, Andrew Mark David Richardson
1998	—	`conf`	CMOS pipelined A/D converters with concurrent error detection capability. ICECS Eduardo J. Peralías, Adoración Rueda, José L. Huertas
1998	A	`conf`	DfT and on-line test of high-performance data converters: a practical case. ITC Eduardo J. Peralías, Adoración Rueda, Juan A. Prieto, José L. Huertas
1997	Misc	`conf`	A DFT Technique for Analog-to-Digital Converters with digital correction. VTS Eduardo J. Peralías, Adoración Rueda, José L. Huertas
1997	A*	`conf`	SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor Systems. DAC Salvador Mir, Adoración Rueda, Thomas Olbrich, Eduardo J. Peralías, José Luis Huertas
1995	A	`conf`	Statistical behavioral modeling and characterization of A/D converters. ICCAD Eduardo J. Peralías, Adoración Rueda, José Luis Huertas