Eduardo I. Boemo

30 papers A 3B 7Journal 9Unranked 11
YearRankTypeTitle / Venue / Authors
2020 J jnl
Real-Time Reconfigurable Processor to Detect Similarities in Compressed Video Using Generalized Hough Transformation.
IEEE Trans. Circuits Syst. Video Technol.
Sergio Ruben Geninatti, Eduardo I. Boemo
2019 J jnl
A Framework to Compare Estimated and Measured Power Consumption on FPGAs.
J. Low Power Electron.
Juan P. Oliver, Federico Favaro, Eduardo I. Boemo
2017 J jnl
A Low Cost System for Self Measurements of Power Consumption in Field Programmable Gate Arrays.
J. Low Power Electron.
Juan P. Oliver, Francisco Veirano, Diego A. Bouvier, Eduardo I. Boemo
2013 J jnl
Self-Reconfigurable Constant Multiplier for FPGA.
ACM Trans. Reconfigurable Technol. Syst.
Javier Hormigo, Gabriel Caffarena, Juan P. Oliver, Eduardo I. Boemo
2013 — conf
Tracking the pipelining-power rule along the FPGA technical literature.
FPGAworld
Eduardo I. Boemo, Juan P. Oliver, Gabriel Caffarena
2008 — conf
Arithmetic Operations and Their Energy Consumption in the Nios II Embedded Processor.
ReConFig
David M. Cambre, Eduardo I. Boemo, Elias Todorovich
2007 J jnl
Editorial - Field-programmable logic and applications.
IET Comput. Digit. Tech.
Philip Heng Wai Leong, Andreas Koch, Eduardo I. Boemo
2006 B conf
A-B Nodes Classification for Power Estimation.
FPL
Elias Todorovich, Eduardo I. Boemo
2006 — conf
Evaluation of a Locomotion Algorithm for Worm-Like Robots on FPGA-Embedded Processors.
ARC
Juan González-Gómez, Iván González, Francisco J. Gomez-Arribas, Eduardo I. Boemo
2005 — conf
FPGA implementation of a synchronous and self-timed neuroprocessor.
ReConFig
Juan José Raygoza-Panduro, Susana Ortega-Cisneros, Eduardo I. Boemo
2005 — conf
Motion of Minimal Configurations of a Modular Robot: Sinusoidal, Lateral Rolling and Lateral Shift.
CLAWAR
Juan González-Gómez, Eduardo I. Boemo
2005 — conf
Rapid prototyping of a self-timed ALU with FPGAs.
ReConFig
Susana Ortega-Cisneros, Juan José Raygoza-Panduro, Juan Suardíaz Muro, Eduardo I. Boemo
2005 B conf
Statistical Power Estimation for FPGA.
FPL
Elias Todorovich, Fabian Angarita, Javier Valls, Eduardo I. Boemo
2004 J jnl
Digital Signal Transmission with Chaotic Encryption: Design and Evaluation of a FPGA Realization
CoRR
C. M. Gonzalez, Hilda A. Larrondo, C. A. Gayoso, Leonardo J. Arnone, Eduardo I. Boemo
2004 A conf
Making visible the thermal behaviour of embedded microprocessors on FPGAs: a progress report.
FPGA
Sergio López-Buedo, Eduardo I. Boemo
2004 — conf
Power Aware Dividers in FPGA.
PATMOS
Gustavo Sutter, Jean-Pierre Deschamps, Gery Bioul, Eduardo I. Boemo
2004 A conf
Power analysis and estimation tool integrated with XPOWER.
FPGA
Elias Todorovich, Eduardo I. Boemo, Francisco Cardells-Tormo, Javier Valls
2003 J jnl
Efficient FPGA-implementation of two's complement digit-serial/parallel multipliers.
IEEE Trans. Circuits Syst. II Express Briefs
Javier Valls, Eduardo I. Boemo
2002 B conf
A Tool for Activity Estimation in FPGAs.
FPL
Elias Todorovich, M. Gilabert, Gustavo Sutter, Sergio López-Buedo, Eduardo I. Boemo
2002 B conf
FSM Decomposition for Low Power in FPGA.
FPL
Gustavo Sutter, Elias Todorovich, Sergio López-Buedo, Eduardo I. Boemo
2002 — conf
Low-Power FSMs in FPGA: Encoding Alternatives.
PATMOS
Gustavo Sutter, Elias Todorovich, Sergio López-Buedo, Eduardo I. Boemo
2002 B conf
Run-Time Reconfiguration to Check Temperature in Custom Computers: An Application of JBits Technology.
FPL
Sergio López-Buedo, Paula Riviere, Pablo Pernas, Eduardo I. Boemo
2000 J jnl
Thermal Testing on Reconfigurable Computers.
IEEE Des. Test Comput.
Sergio López-Buedo, Javier Garrido Salas, Eduardo I. Boemo
1999 — conf
A comparison between lattice, cascade and direct form FIR filter structures by using a FPGA bit-serial distributed arithmetic implementation.
ICECS
Marcos Martínez-Peiró, Javier Valls, T. Sansaloni, A. Perez-Pascual, Eduardo I. Boemo
1999 — conf
Fast FPGA-based pipelined digit-serial/parallel multipliers.
ISCAS (1)
Javier Valls, Trini Sansaloni, Marcos Martínez-Peiró, Eduardo I. Boemo
1998 — conf
Design and FPGA implementation of digit-serial FIR filters.
ICECS
Javier Valls, Marcos M. Peiró, Trinidad Sansaloni, Eduardo I. Boemo
1998 J jnl
Some experiments about wave pipelining on FPGA's.
IEEE Trans. Very Large Scale Integr. Syst.
Eduardo I. Boemo, Sergio López-Buedo, Juan M. Meneses
1997 B conf
Thermal monitoring on FPGAs using ring-oscillators.
FPL
Eduardo I. Boemo, Sergio López-Buedo
1996 A conf
The Wave Pipeline Effect on LUT-Based FPGA Architectures.
FPGA
Eduardo I. Boemo, Sergio López-Buedo, Juan M. Meneses
1995 B conf
Some Notes on Power Management on FPGA-Based Systems.
FPL
Eduardo I. Boemo, Guillermo González de Rivera, Sergio López-Buedo, Juan M. Meneses