Eduardo de la Torre

94 papers A 4B 7C 7Misc 1Journal 30Unranked 44

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	Data-driven modeling of reconfigurable multi-accelerator systems under dynamic workloads. Microprocess. Microsystems Juan Encinas, Alfonso Rodríguez, Andrés Otero, Eduardo de la Torre
2023	J	`jnl`	Dynamically Reconfigurable Variable-precision Sparse-Dense Matrix Acceleration in Tensorflow Lite. CoRR José L. Núñez-Yáñez, Andrés Otero, Eduardo de la Torre
2023	J	`jnl`	Dynamically reconfigurable variable-precision sparse-dense matrix acceleration in Tensorflow Lite. Microprocess. Microsystems José L. Núñez-Yáñez, J. Andrés Otero, Eduardo de la Torre
2023	—	`conf`	Evolutionary FPGA-Based Spiking Neural Networks for Continual Learning. ARC Andrés Otero, Guillermo Sanllorente, Eduardo de la Torre, José L. Núñez-Yáñez
2022	—	`conf`	A Multi-FPGA Scalable Framework for Deep Reinforcement Learning Through Neuroevolution. ARC Javier Laserna, Andrés Otero, Eduardo de la Torre
2022	J	`jnl`	Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs. IEEE Trans. Computers Alfonso Rodríguez, Andrés Otero, Marco Platzner, Eduardo de la Torre
2022	—	`conf`	Extending RISC-V Processor Datapaths with Multi-Grain Reconfigurable Overlays. DCIS Daniel Vázquez, Alfonso Rodríguez, Andrés Otero, Eduardo de la Torre
2022	—	`conf`	Just-In-Time Composition of Reconfigurable Overlays (Invited Talk). PARMA-DITAM@HiPEAC Rafael Zamacola, Andrés Otero, Alfonso Rodríguez, Eduardo de la Torre
2021	J	`jnl`	A Machine-Learning-Based Distributed System for Fault Diagnosis With Scalable Detection Quality in Industrial IoT. IEEE Internet Things J. Rodrigo Marino, Cristian Wisultschew, Andrés Otero, José Manuel Lanza-Gutiérrez, Jorge Portilla, Eduardo de la Torre
2021	J	`jnl`	Multi-grain reconfigurable and scalable overlays for hardware accelerator composition. J. Syst. Archit. Rafael Zamacola, Andrés Otero, Eduardo de la Torre
2021	—	`conf`	Run-Time Monitoring and ML-Based Modeling in Reconfigurable Multi-Accelerator Systems. DCIS Juan Encinas, Alfonso Rodríguez, Andrés Otero, Eduardo de la Torre
2020	—	`conf`	Accelerating a Classic 3D Video Game on Heterogeneous Reconfigurable MPSoCs. ARC Leonardo Suriano, David Lima, Eduardo de la Torre
2020	J	`jnl`	An Integrated Approach and Tool Support for the Design of FPGA-Based Multi-Grain Reconfigurable Systems. IEEE Access Rafael Zamacola, Andrés Otero, Alberto García-Martínez, Eduardo de la Torre
2020	—	`conf`	Automated Toolchain for Enhanced Productivity in Reconfigurable Multi-accelerator Systems. ARC Alberto García Ortiz, Rafael Zamacola, Alfonso Rodríguez, Andrés Otero, Eduardo de la Torre
2020	J	`jnl`	Exploiting Multi-Level Parallelism for Run-Time Adaptive Inverse Kinematics on Heterogeneous MPSoCs. IEEE Access Leonardo Suriano, Andrés Otero, Alfonso Rodríguez, Manuel Sánchez-Renedo, Eduardo de la Torre
2020	J	`jnl`	Run-Time Reconfigurable MPSoC-Based On-Board Processor for Vision-Based Space Navigation. IEEE Access Arturo Perez, Alfonso Rodríguez, Andrés Otero, David González Arjona, Álvaro Jiménez-Peralo, Miguel Ángel Verdugo, Eduardo de la Torre
2019	—	`conf`	A Dataflow Implementation of Inverse Kinematics on Reconfigurable Heterogeneous MPSoC. CPS Summer School, PhD Workshop Luca Fanni, Leonardo Suriano, Claudio Rubattu, Pablo Sánchez, Eduardo de la Torre, Francesca Palumbo
2019	—	`conf`	Artificial Vision on Edge IoT Devices: A Practical Case for 3D Data Classification. DCIS Cristian Wisultschew, Andrés Otero, Jorge Portilla, Eduardo de la Torre
2019	Misc	`conf`	Automated Tool and Runtime Support for Fine-Grain Reconfiguration in Highly Flexible Reconfigurable Systems. FCCM Rafael Zamacola, Alberto García-Martínez, Javier Mora, Andrés Otero, Eduardo de la Torre
2019	J	`jnl`	DAMHSE: Programming heterogeneous MPSoCs with hardware acceleration using dataflow-based design space exploration and automated rapid prototyping. Microprocess. Microsystems Leonardo Suriano, Florian Arrestier, Alfonso Rodríguez, Julien Heulot, Karol Desnos, Maxime Pelcat, Eduardo de la Torre
2019	—	`conf`	Data Transfer Modeling and Optimization in Reconfigurable Multi-Accelerator Systems. ReCoSoC Alberto García Ortiz, Alfonso Rodríguez, Andrés Otero, Eduardo de la Torre
2019	—	`conf`	Hardware Accelerator for Ethanol Detection in Water Media based on Machine Learning Techniques. DCIS Rodrigo Marino, Sergio Quintero, José Manuel Lanza-Gutiérrez, Teresa Riesgo, Miguel Holgado, Jorge Portilla, Eduardo de la Torre
2019	—	`conf`	Hardware/Software Self-adaptation in CPS: The CERBERO Project Approach. SAMOS Francesca Palumbo, Tiziana Fanni, Carlo Sau, Alfonso Rodríguez, Daniel Madroñal, Karol Desnos, Antoine Morvan, Maxime Pelcat, Claudio Rubattu, Raquel Lazcano, Luigi Raffo, Eduardo de la Torre, Eduardo Juárez, César Sanz, Pablo Sanchez de Rojas
2019	J	`jnl`	On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming. Genet. Program. Evolvable Mach. Javier Mora, Rubén Salvador, Eduardo de la Torre
2019	J	`jnl`	Scalable Hardware-Based On-Board Processing for Run-Time Adaptive Lossless Hyperspectral Compression. IEEE Access Alfonso Rodríguez, Lucana Santos, Roberto Sarmiento, Eduardo de la Torre
2018	J	`jnl`	A Runtime-Scalable and Hardware-Accelerated Approach to On-Board Linear Unmixing of Hyperspectral Images. Remote. Sens. Alberto García Ortiz, Alfonso Rodríguez, Raúl Guerra, Sebastián López, Andrés Otero, Roberto Sarmiento, Eduardo de la Torre
2018	—	`conf`	A Unified Hardware/Software Monitoring Method for Reconfigurable Computing Architectures Using PAPI. ReCoSoC Leonardo Suriano, Daniel Madroñal, Alfonso Rodríguez, Eduardo Juárez, César Sanz, Eduardo de la Torre
2018	J	`jnl`	Accelerating the evolution of a systolic array-based evolvable hardware system. Microprocess. Microsystems Javier Mora, Eduardo de la Torre
2018	J	`jnl`	FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo Sensors Alfonso Rodríguez, Juan Valverde, Jorge Portilla, Andrés Otero, Teresa Riesgo, Eduardo de la Torre
2018	—	`conf`	IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx Vivado. ReConFig Rafael Zamacola, Alberto García-Martínez, Javier Mora, Andrés Otero, Eduardo de la Torre
2018	—	`conf`	Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber-Physical Systems. ReConFig Tiziana Fanni, Alfonso Rodríguez, Carlo Sau, Leonardo Suriano, Francesca Palumbo, Luigi Raffo, Eduardo de la Torre
2018	—	`conf`	Performance Analysis of SEE Mitigation Techniques on Zynq Ultrascale + Hardened Processing Fabrics. AHS Arturo Perez, Andrés Otero, Eduardo de la Torre
2017	—	`conf`	Analysis of a heterogeneous multi-core, multi-hw-accelerator-based system designed using PREESM and SDSoC. ReCoSoC Leonardo Suriano, Alfonso Rodríguez, Karol Desnos, Maxime Pelcat, Eduardo de la Torre
2017	A	`conf`	Cross-layer design of reconfigurable cyber-physical systems. DATE Michael Masin, Francesca Palumbo, Hans Myrhaug, J. A. de Oliveira Filho, M. Pastena, Maxime Pelcat, Luigi Raffo, Francesco Regazzoni, A. A. Sanchez, Antonella Toffetti, Eduardo de la Torre, Katiuscia Zedda
2017	—	`conf`	Dynamic reconfiguration under RTEMS for fault mitigation and functional adaptation in SRAM-based SoPCs for space systems. AHS Arturo Perez, Leonardo Suriano, Andrés Otero, Eduardo de la Torre
2016	J	`jnl`	A scalable H.264/AVC deblocking filter architecture. J. Real Time Image Process. Teresa Cervero, Andrés Otero, Sebastián López, Eduardo de la Torre, Gustavo M. Callicó, Teresa Riesgo, Roberto Sarmiento
2016	J	`jnl`	Introduction to the Special Section on FPGAs Technology and Applications. Comput. Electr. Eng. René Cumplido, Peter Athanas, Eduardo de la Torre
2015	—	`conf`	Adaptive reconfigurable voting for enhanced reliability in medium-grained fault tolerant architectures. AHS Filip Veljkovic, Teresa Riesgo, Eduardo de la Torre
2015	—	`conf`	Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAs. ReConFig Alfonso Rodríguez, Juan Valverde, Eduardo de la Torre
2015	—	`conf`	Execution modeling in self-aware FPGA-based architectures for efficient resource management. ReCoSoC Alfonso Rodríguez, Juan Valverde, Cesar Castanares, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo
2015	—	`conf`	Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs. ReCoSoC Javier Mora, Andrés Otero, Eduardo de la Torre, Teresa Riesgo
2015	J	`jnl`	Introduction to Special issue on Reconfigurable computing and FPGAs. Microprocess. Microsystems René Cumplido, Eduardo de la Torre, Claudia Feregrino-Uribe, Michael J. Wirthlin
2015	J	`jnl`	Letter from the guest editors of the special issue on DCIS 2014. Microprocess. Microsystems Eduardo de la Torre, Jorge Portilla, Teresa Riesgo
2015	C	`conf`	Live demonstration: A dynamically adaptable image processing application running in an FPGA-based WSN platform. ISCAS Alfonso Rodríguez, Juan Valverde, Cesar Castanares, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo
2015	—	`conf`	Message from the chairs. ReCoSoC Alberto García Ortiz, Daniel Gregorek, Eduardo de la Torre, Juha Plosila
2015	J	`jnl`	Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis. IET Inf. Secur. Wei He, Shivam Bhasin, Andrés Otero, Tarik Graba, Eduardo de la Torre, Jean-Luc Danger
2014	C	`conf`	A Progressive Dual-Rail Routing Repair Approach for FPGA Implementation of Crypto Algorithm. ISPEC Chenyang Tu, Wei He, Neng Gao, Eduardo de la Torre, Zeyi Liu, Limin Liu
2014	B	`conf`	A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems. FPL Juan Valverde, Alfonso Rodríguez, Julio Camarero, Andrés Otero, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo
2014	—	`conf`	A run time adaptive architecture to trade-off performance for fault tolerance applied to a DVB on-board processor. AHS Filip Veljkovic, Teresa Riesgo, Eduardo de la Torre, Raul Regada, Luis Berrojo
2014	J	`jnl`	Customized and automated routing repair toolset towards side-channel analysis resistant dual rail logic. Microprocess. Microsystems Wei He, Andrés Otero, Eduardo de la Torre, Teresa Riesgo
2014	—	`conf`	Dynamic management of multikernel multithread accelerators using Dynamic Partial Reconfiguration. ReCoSoC Alfonso Rodríguez, Juan Valverde, Eduardo de la Torre, Teresa Riesgo
2014	J	`jnl`	Introduction to Special issue on FPGA Devices and Applications. Microprocess. Microsystems Peter M. Athanas, René Cumplido, Claudia Feregrino-Uribe, Eduardo de la Torre
2014	J	`jnl`	Introduction to the special issue on FPGA Technology and Applications. Comput. Electr. Eng. Peter Athanas, René Cumplido, Eduardo de la Torre
2014	—	`conf`	Power-aware multi-objective evolvable hardware system on an FPGA. AHS Blanca López, Juan Valverde, Eduardo de la Torre, Teresa Riesgo
2014	—	`ed.`	Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, DASIP 2014, Madrid, Spain, October 8-10, 2014 DASIP Eduardo de la Torre, Sébastien Pillement
2013	—	`conf`	A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing Arrays. IPDPS Workshops Angel Gallego, Javier Mora, Andrés Otero, Rubén Salvador, Eduardo de la Torre, Teresa Riesgo
2013	—	`conf`	A noise-agnostic self-adaptive image processing application based on evolvable hardware. DASIP Javier Mora, Angel Gallego, Andrés Otero, Blanca López, Eduardo de la Torre, Teresa Riesgo
2013	—	`conf`	A scalable evolvable hardware processing array. ReConFig Angel Gallego, Javier Mora, Andrés Otero, Eduardo de la Torre, Teresa Riesgo
2013	B	`conf`	A self-adaptive image processing application based on evolvable and scalable hardware. FPL Angel Gallego, Javier Mora, Andrés Otero, Blanca López, Eduardo de la Torre, Teresa Riesgo
2013	—	`conf`	Noise-agnostic adaptive image filtering without training references on an evolvable hardware platform. DASIP Javier Mora, Angel Gallego, Andrés Otero, Eduardo de la Torre, Teresa Riesgo
2013	J	`jnl`	Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing. IEEE Trans. Computers Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina
2012	—	`conf`	An Interleaved EPE-Immune PA-DPL Structure for Resisting Concentrated EM Side Channel Attacks on FPGA Implementation. COSADE Wei He, Eduardo de la Torre, Teresa Riesgo
2012	—	`conf`	Automatic generation of identical routing pairs for FPGA implemented DPL logic. ReConFig Wei He, Andrés Otero, Eduardo de la Torre, Teresa Riesgo
2012	—	`conf`	Dreams: A tool for the design of dynamically reconfigurable embedded and modular systems. ReConFig Andrés Otero, Eduardo de la Torre, Teresa Riesgo
2012	C	`conf`	FASTCUDA: Open Source FPGA Accelerator & Hardware-Software Codesign Toolset for CUDA Kernels. DSD Iakovos Mavroidis, Ioannis Mavroidis, Ioannis Papaefstathiou, Luciano Lavagno, Mihai T. Lazarescu, Eduardo de la Torre, Florian Schäfer
2012	B	`conf`	Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration. FPL Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina
2012	—	`conf`	Power management techniques in an FPGA-based WSN node for high performance applications. ReCoSoC Miguel Lombardo, Julio Camarero, Juan Valverde, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo
2012	J	`jnl`	Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks. Sensors Juan Valverde, Andrés Otero, Miguel Lopez, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo
2011	—	`conf`	A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations. ReConFig Wei He, Eduardo de la Torre, Teresa Riesgo
2011	—	`conf`	A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems. AHS Andrés Otero, Rubén Salvador, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina
2011	A	`conf`	A novel scalable Deblocking Filter architecture for H.264/AVC and SVC video codecs. ICME Teresa Cervero, Andrés Otero, Sebastián López, Eduardo de la Torre, Gustavo M. Callicó, Roberto Sarmiento, Teresa Riesgo
2011	—	`conf`	Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support. AHS Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina
2011	—	`conf`	Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems. ReConFig Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Lukás Sekanina, Teresa Riesgo
2011	B	`conf`	Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs. FPL Andrés Otero, Eduardo de la Torre, Teresa Riesgo, Teresa Cervero, Sebastián López, Gustavo M. Callicó, Roberto Sarmiento
2010	C	`conf`	A Modular Peripheral to Support Self-Reconfiguration in SoCs. DSD Andrés Otero, Angel Morales-Cas, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo
2010	J	`jnl`	Adaptable Security in Wireless Sensor Networks by Using Reconfigurable ECC Hardware Coprocessors. Int. J. Distributed Sens. Networks Jorge Portilla, Andrés Otero, Eduardo de la Torre, Teresa Riesgo, Oliver Stecklina, Steffen Peter, Peter Langendörfer
2010	—	`conf`	Generic Systolic Array for Run-Time Scalable Cores. ARC Andrés Otero, Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo
2010	J	`jnl`	Reconfigurable Networks on Chip: DRNoC architecture. J. Syst. Archit. Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo
2010	B	`conf`	Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs. FPL Andrés Otero, Eduardo de la Torre, Teresa Riesgo, Yana Esteves Krasteva
2008	—	`conf`	A Fast Emulation-Based NoC Prototyping Framework. ReConFig Yana Esteves Krasteva, Francisco Criado, Eduardo de la Torre, Teresa Riesgo
2007	J	`jnl`	A digital system to emulate wireless networks. IET Comput. Digit. Tech. Eduardo Peña, Eduardo de la Torre, Angel de Castro, Teresa Riesgo
2007	C	`conf`	Reconfigurable Heterogeneous Communications and Core Reallocation for Dynamic HW Task Management. ISCAS Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo
2006	J	`jnl`	A Modular Architecture for Nodes in Wireless Sensor Networks. J. Univers. Comput. Sci. Jorge Portilla, Angel de Castro, Eduardo de la Torre, Teresa Riesgo
2006	—	`conf`	Partial Reconfiguration for Core Reallocation and Flexible Communications. ReCoSoC Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo
2006	B	`conf`	Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems. FPL Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo, Didier Joly
2005	—	`conf`	Flexible Core Reallocation for Virtex II Structures. ERSA Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo
2005	C	`conf`	Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAs. IEEE International Workshop on Rapid System Prototyping Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo
2004	B	`conf`	Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion. FPL Mario García-Valderas, Eduardo de la Torre, F. Ariza, Teresa Riesgo
2000	C	`conf`	Highly Configurable Control Boards: A Tool and a Design Experience. IEEE International Workshop on Rapid System Prototyping Eduardo de la Torre, Teresa Riesgo, Javier Uceda, E. Macip, M. Rizzi
1999	J	`jnl`	Design methodologies based on hardware description languages. IEEE Trans. Ind. Electron. Teresa Riesgo, Yago Torroja, Eduardo de la Torre
1998	A	`conf`	Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models. DATE Teresa Riesgo, Yago Torroja, Eduardo de la Torre, Javier Uceda
1996	—	`conf`	Model generation of test logic for macrocell based designs. EURO-DAC Eduardo de la Torre, J. Calvo, Javier Uceda
1993	—	`conf`	A dynamic communication strategy for the distributed ATPG system DPLATON. EURO-DAC Maria José Aguado, Miguel Miranda, Eduardo de la Torre, Carlos A. López-Barrio
1993	A	`conf`	Distributed Implementation of an ATPG System Using Dynamic Fault Allocation. ITC Maria José Aguado, Eduardo de la Torre, Miguel Miranda, Carlos A. López-Barrio