Eduard Cerny - RankMe

80 papers A* 5A 4B 3C 8Misc 1Journal 35Unranked 24

Year	Rank	Type	Title / Venue / Authors
2005	—	`conf`	Supporting sequential assumptions in hybrid verification. ASP-DAC Eduard Cerny, Ashvin Dsouza, Kevin Harer, Pei-Hsin Ho, Hi-Keung Tony Ma
2004	J	`jnl`	MDG-Based State Enumeration By Retiming And Circuit Transformation. J. Circuits Syst. Comput. Otmane Aït Mohamed, Xiaoyu Song, Eduard Cerny, Sofiène Tahar, Zijian Zhou
2004	J	`jnl`	Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs (MDGs). Comput. J. Ying Xu, Xiaoyu Song, Eduard Cerny, Otmane Aït Mohamed
2003	J	`jnl`	On the non-termination of M-based abstract state enumeration. Theor. Comput. Sci. Otmane Aït Mohamed, Xiaoyu Song, Eduard Cerny
2002	—	`conf`	Term ordering problem on MDG. ACM Great Lakes Symposium on VLSI Yi Feng, Eduard Cerny
2002	—	`conf`	Variable ordering on multiway decision graphs. ISCAS (5) Yi Feng, Eduard Cerny
2000	—	`conf`	Compositional verification of an ATM switch module using interface recognizer/suppliers (IRS). HLDVT M. S. Jahanpour, Eduard Cerny
2000	B	`conf`	Model Reductions and a Case Study. FMCAD Jin Hou, Eduard Cerny
1999	—	`conf`	Improving Termination of MDG-Based Abstract State Enumeration via Term Schematization. SMC@FLoC Sophie Renault, Eduard Cerny
1999	J	`jnl`	Modeling and formal verification of the Fairisle ATM switch fabricusing MDGs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sofiène Tahar, Xiaoyu Song, Eduard Cerny, Zijian Zhou, Michel Langevin, Otmane Aït Mohamed
1999	—	`conf`	Practical Application of Formal Verification Techniques on a Frame Mux/Demux Chip from Nortel Semiconductors. CHARME Ying Xu, Eduard Cerny, Allan Silburt, A. Coady, Ying Liu, Philip Pownall
1999	—	`conf`	Synthesis of checker EFSMs from timing diagram specifications. ISCAS (1) E. K. Ogoubi, Eduard Cerny
1999	J	`jnl`	Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Samir Boubezari, Eduard Cerny, Bozena Kaminska, Benoit Nadeau-Dostie
1999	C	`conf`	Verification of Real Time Controllers Against Timing Diagram Specifications Using Constraint Logic Programming. ICCD Eduard Cerny, Fen Jin
1999	J	`jnl`	Worst case tolerance analysis and CLP-based multifrequency test generation for analog circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Abdessatar Abderrahman, Eduard Cerny, Bozena Kaminska
1998	—	`conf`	MDG-based Verification by Retiming and Combinational Transformations. Great Lakes Symposium on VLSI Otmane Aït Mohamed, Eduard Cerny, Xiaoyu Song
1998	B	`conf`	Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints. FMCAD Fen Jin, Henrik Hulgaard, Eduard Cerny
1998	A*	`conf`	Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs. CAV Ying Xu, Eduard Cerny, Xiaoyu Song, Francisco Corella, Otmane Aït Mohamed
1998	A	`conf`	Propagation of Last-Transition-Time Constraints in Gate-Level Timing Analysis. DATE Maroun Kassab, Eduard Cerny, Sidi Aourid, Thomas H. Krodel
1998	J	`jnl`	Semantics and verification of action diagrams with linear timing. ACM Trans. Design Autom. Electr. Syst. Karim Khordoc, Eduard Cerny
1998	—	`conf`	Synthesis of interface controllers from timing diagram specifications. CICC Abdelhalim El-Aboudi, El Mostapha Aboulhamid, Eduard Cerny
1998	—	`conf`	Verification of Real Time Controllers Against Timing Diagram Specifications Using Constraint Logic Programming. EUROMICRO Eduard Cerny, Fen Jin
1997	Misc	`conf`	CLP-based Multifrequency Test Generation for Analog Circuits. VTS Abdessatar Abderrahman, Eduard Cerny, Bozena Kaminska
1997	—	`conf`	Interface timing verification with delay correlation using constraint logic programming. ED&TC Pierre Girodias, Eduard Cerny
1997	J	`jnl`	Model partitioning and the performance of distributed timewarp simulation of logic circuits. Simul. Pract. Theory Jocelyn Cloutier, Eduard Cerny, F. Guertin
1997	J	`jnl`	Multiway Decision Graphs for Automated Hardware Verification. Formal Methods Syst. Des. Francisco Corella, Zijian Zhou, Xiaoyu Song, Michel Langevin, Eduard Cerny
1997	—	`conf`	On the non-termination of MDGs-based abstract state enumeration. CHARME Otmane Aït Mohamed, Xiaoyu Song, Eduard Cerny
1997	J	`jnl`	Solving Linear, Min and Max Constraint Systems Using CLP Based on Relational Interval Arithmetic. Theor. Comput. Sci. Pierre Girodias, Eduard Cerny, William J. Older
1997	—	`conf`	Verification with Abstract State Machines Using MDGs. Formal Hardware Verification Eduard Cerny, Francisco Corella, Michel Langevin, Xiaoyu Song, Sofiène Tahar, Zijian Zhou
1996	J	`jnl`	A recursive technique for computing lower-bound performance of schedules. ACM Trans. Design Autom. Electr. Syst. Michel Langevin, Eduard Cerny
1996	C	`conf`	Behavioral Verification of an ATM Switch Fabric using Implicit Abstract State Enumeration. ICCD Michel Langevin, Sofiène Tahar, Zijian Zhou, Xiaoyu Song, Eduard Cerny
1996	—	`conf`	Bounding Switching Activity in CMOS Circuits Using Constraint Resolution. ED&TC Jindrich Zejda, Eduard Cerny, S. Shenoy, Nicholas C. Rumin
1996	J	`jnl`	Efficient generation of diagonal constraints for 2-D mask compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Guy Bois, Eduard Cerny
1996	—	`conf`	Formal Verification of an ATM Switch Fabric using Multiway Decision Graphs. Great Lakes Symposium on VLSI Sofiène Tahar, Zijian Zhou, Xiaoyu Song, Eduard Cerny, Michel Langevin
1996	B	`conf`	Formal Verification of the Island Tunnel Controller Using Multiway Decision Graphs. FMCAD Zijian Zhou, Xiaoyu Song, Sofiène Tahar, Eduard Cerny, Francisco Corella, Michel Langevin
1996	A*	`conf`	MDG Tools for the Verification of RTL Designs. CAV K. D. Anon, N. Boulerice, Eduard Cerny, Francisco Corella, Michel Langevin, Xiaoyu Song, Sofiène Tahar, Ying Xu, Zijian Zhou
1996	J	`jnl`	Optimization-based multifrequency test generation for analog circuits. J. Electron. Test. Abdessatar Abderrahman, Bozena Kaminska, Eduard Cerny
1995	—	`conf`	Partitioning transition relations efficiently and automatically. Great Lakes Symposium on VLSI Zijian Zhou, Xiaoyu Song, Francisco Corella, Eduard Cerny, Michel Langevin
1995	A	`conf`	Solving Linear, Min and Max Constraint Systems Using CLP based on Relational Interval Arithmetic. CP Pierre Girodias, Eduard Cerny, William J. Older
1995	—	`conf`	State enumeration with abstract descriptions of state machines. CHARME Francisco Corella, Michel Langevin, Eduard Cerny, Zijian Zhou, Xiaoyu Song
1994	—	`conf`	An Extended OBDD Representation for Extended FSMs. EDAC-ETC-EUROASIC Michel Langevin, Eduard Cerny
1994	J	`jnl`	Fault Tolerance in a Class of Sorting Networks. IEEE Trans. Computers Jianli Sun, Eduard Cerny, Jan Gecsei
1994	—	`conf`	Gate-level timing verification using waveform narrowing. EURO-DAC Jindrich Zejda, Eduard Cerny
1994	—	`conf`	Local microcode generation in system design. Code Generation for Embedded Processors Michel Langevin, Eduard Cerny, Jörg Wilberg, Heinrich Theodor Vierhaus
1994	C	`conf`	Modeling Cell Processing Hardware with Action Diagrams. ISCAS Karim Khordoc, Eduard Cerny
1994	J	`jnl`	Use of Fault Dropping for Multiple Fault Analysis. IEEE Trans. Computers Younès Karkouri, El Mostapha Aboulhamid, Eduard Cerny, Alain Verreault
1993	C	`conf`	A Recursive Technique for Computing Lower-Bound Performance of Schedules. ICCD Michel Langevin, Eduard Cerny
1993	—	`conf`	Integrating Behavior and Timing in Executable Specifications. CHDL Karim Khordoc, Mario Dufresne, Eduard Cerny, P. A. Babkine, Allan Silburt
1993	J	`jnl`	On the generation of test patterns for multiple faults. J. Electron. Test. El Mostapha Aboulhamid, Younès Karkouri, Eduard Cerny
1992	J	`jnl`	Accuracy of magnitude-class calculations in switch-level modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Eduard Cerny, John P. Hayes, Nicholas C. Rumin
1992	J	`jnl`	Algorithm for the graph-partitioning problem using a problem transformation method. Comput. Aided Des. Mohamed Meknassi, El Mostapha Aboulhamid, Eduard Cerny
1992	C	`conf`	Verification of I/O Trace Set Inclusion for a Class of Non-Deterministic Finite State Machines. ICCD Eduard Cerny
1991	C	`conf`	A Compositional Transformation for Formal Verification. ICCD Eduard Cerny
1991	A	`conf`	A Stimulus/Response System Based on Hierarchical Timing Diagrams. ICCAD Karim Khordoc, Mario Dufresne, Eduard Cerny
1991	J	`jnl`	A recursive technique for computing delays in series-parallel MOS transistor circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jean Paul Caisso, Eduard Cerny, Nicholas C. Rumin
1991	A*	`conf`	Comparing Generic State Machines. CAV Michel Langevin, Eduard Cerny
1991	—	`conf`	Design by similarity using transaction modeling and statistical techniques. EURO-DAC Anas Kabbaj, Eduard Cerny, Michel R. Dagenais, François Bouthillier
1990	J	`jnl`	Fault-tolerance in balanced sorting networks. J. Electron. Test. Jianli Sun, Jan Gecsei, Eduard Cerny
1990	A	`conf`	Tautology Checking Using Cross-Controllability and Cross-Observability Relations. ICCAD Eduard Cerny, C. Mauras
1989	C	`conf`	Magnitude classes in switch-level modeling. ICCD Eduard Cerny, John P. Hayes, Nicholas C. Rumin
1988	C	`conf`	A class of fault-tolerant cellular permutation networks. ICCD Mohsine Eleuldj, El Mostapha Aboulhamid, Eduard Cerny
1988	J	`jnl`	An Algebraic Model for Asynchronous Circuits Verification. IEEE Trans. Computers Christian Berthet, Eduard Cerny
1988	J	`jnl`	Built-in self-test of a CMOS ALU. IEEE Des. Test Eduard Cerny, El Mostapha Aboulhamid, Guy Bois, Jocelyn Cloutier
1988	J	`jnl`	Functional Description of Connector-Switch-Attenuator Networks. IEEE Trans. Computers Eduard Cerny, Jan Gecsei
1987	J	`jnl`	A Test Design Methodology for Protocol Testing. IEEE Trans. Software Eng. Behçet Sarikaya, Gregor von Bochmann, Eduard Cerny
1987	A*	`conf`	CHESHIRE: An Object-Oriented Integration of VLSI CAD Tools. DAC Louis-Philippe Demers, P. Jacques, S. Fauvel, Eduard Cerny
1987	J	`jnl`	Self-Adjusting Networks for VLSI Simulation. IEEE Trans. Computers Jan Gecsei, Eduard Cerny
1985	A*	`conf`	An object-oriented swicth-level simulator. DAC C. Roy, Louis-Philippe Demers, Eduard Cerny, Jan Gecsei
1985	J	`jnl`	Simulation of MOS Circuits by Decision Diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Eduard Cerny, Jan Gecsei
1984	J	`jnl`	Built-In Testing of One-Dimensional Unilateral Iterative Arrays. IEEE Trans. Computers El Mostapha Aboulhamid, Eduard Cerny
1984	J	`jnl`	Some issues in protocol implementation testing. Comput. Commun. Rev. Eduard Cerny
1984	—	`conf`	Use of Formal Specifications for Protocol Design, Implementation and Testing. PSTV Gregor von Bochmann, Eduard Cerny, George Walter Gerber, Rachida Dssouli, Michel Maksud, B. H. Phan, Behçet Sarikaya, Jean-Marc Serre
1983	J	`jnl`	A Class of Test Generators for Built-In Testing. IEEE Trans. Computers El Mostapha Aboulhamid, Eduard Cerny
1982	J	`jnl`	Experience with Formal Specifications Using an Extended State Transition Model. IEEE Trans. Commun. Gregor von Bochmann, Eduard Cerny, Michel Gagné, Claude Jard, Alain Léveillé, Clement Lacaille, Michel Maksud, K. S. Raghunathan, Behçet Sarikaya
1982	—	`conf`	Some Experience with the Use of Formal Specifications. PSTV Gregor von Bochmann, Eduard Cerny, Michel Gagné, Claude Jard, Alain Léveillé, Clement Lacaille, Michel Maksud, K. S. Raghunathan, Behçet Sarikaya
1979	J	`jnl`	Synthesis of Minimal Binary Decision Trees. IEEE Trans. Computers Eduard Cerny, Daniel Mange, Eduardo Sanchez
1978	J	`jnl`	Controllability and Fault Observability in Modular Combinational Circuits. IEEE Trans. Computers Eduard Cerny
1977	J	`jnl`	An Approach to Unified Methodology of Combinational Switching Circuits. IEEE Trans. Computers Eduard Cerny, Miguel A. Marin
1976	J	`jnl`	Comments on "Equational Logic". IEEE Trans. Computers Eduard Cerny
1974	J	`jnl`	A Computer Algorithm for the Synthesis of Memoryless Logic Circuits. IEEE Trans. Computers Eduard Cerny, Miguel A. Marin