Edson I. Moreno

12 papers A 1C 4Journal 4Unranked 3
YearRankTypeTitle / Venue / Authors
2026 J jnl
DEMC: A dynamic multi-ECC memory controller with per-block adaptation.
Integr.
Marco P. Stefani, Felipe G. A. e Silva, Jarbas Silveira, Giovanna Borba, Luthero Vargas, Edson I. Moreno, César A. M. Marcon
2014 C conf
A monitored NoC with runtime path adaptation.
ISCAS
Edson I. Moreno, Thais Webber, César A. M. Marcon, Fernando Moraes, Ney Calazans
2014 J jnl
MoNoC: A monitored network on chip with path adaptation mechanism.
J. Syst. Archit.
Edson I. Moreno, Thais Webber, César A. M. Marcon, Fernando Gehm Moraes, Ney Laert Vilar Calazans
2013 — conf
Determining the test sources/sinks for NoC TAMs.
ISVLSI
Alexandre M. Amory, Edson I. Moreno, Fernando Moraes, Marcelo Lubaszewski
2012 C conf
Buffer depth and traffic influence on 3D NoCs performance.
RSP
Yan Ghidini, Thais Webber, Edson I. Moreno, Fernando Grando, Rubem Dutra Ribeiro Fagundes, César A. M. Marcon
2012 — conf
Topological impact on latency and throughput: 2D versus 3D NoC comparison.
SBCCI
Yan Ghidini, Thais Webber, Edson I. Moreno, Ivan Quadros, Rubem Dutra Ribeiro Fagundes, César A. M. Marcon
2011 C conf
Arbitration and routing impact on NoC design.
International Symposium on Rapid System Prototyping
Edson I. Moreno, César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes
2011 J jnl
CAFES: A framework for intrachip application modeling and communication architecture design.
J. Parallel Distributed Comput.
César A. M. Marcon, Ney Calazans, Edson I. Moreno, Fernando Moraes, Fabiano Hessel, Altamiro Amadeu Susin
2007 C conf
Evaluation of Algorithms for Low Energy Mapping onto NoCs.
ISCAS
César A. M. Marcon, Edson I. Moreno, Ney Laert Vilar Calazans, Fernando Gehm Moraes
2007 J jnl
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture
CoRR
Alexandre M. Amory, Marcelo Lubaszewski, Fernando Gehm Moraes, Edson I. Moreno
2005 A conf
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture.
DATE
Alexandre M. Amory, Marcelo Lubaszewski, Fernando Gehm Moraes, Edson I. Moreno
2003 — conf
From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study.
SBCCI
Ney Laert Vilar Calazans, Edson I. Moreno, Fabiano Hessel, Vitor M. da Rosa, Fernando Moraes, Everton Carara