Edouard Giacomin

28 papers A* 3A 1B 1C 8Journal 8Unranked 7

Year	Rank	Type	Title / Venue / Authors
2023	J	`jnl`	3D SRAM Macro Design in 3D Nanofabric Process Technology. IEEE Trans. Circuits Syst. I Regul. Pap. Dawit Burusie Abdi, Shairfe Muhammad Salahuddin, Jürgen Bömmels, Edouard Giacomin, Pieter Weckx, Julien Ryckaert, Geert Hellings, Francky Catthoor
2023	J	`jnl`	Low Latency SEU Detection in FPGA CRAM With In-Memory ECC Checking. IEEE Trans. Circuits Syst. I Regul. Pap. Aurélien Alacchi, Edouard Giacomin, Scott Temple, Roman Gauchi, Michael J. Wirthlin, Pierre-Emmanuel Gaillardon
2023	J	`jnl`	Smart-Redundancy With In Memory ECC Checking: Low-Power SEE-Resistant FPGA Architectures. IEEE Trans. Very Large Scale Integr. Syst. Aurélien Alacchi, Edouard Giacomin, Roman Gauchi, Szymon Kulis, Pierre-Emmanuel Gaillardon
2021	C	`conf`	A 12-pA Resolution Sigma Delta ADC Topology for Chemiresistive Sensor-Based Applications. VLSI-SoC Matthieu Couriol, Edouard Giacomin, Pierre-Emmanuel Gaillardon
2021	—	`conf`	A First Approach in Using Super-Steep-Subthreshold-Slope Field-Effect Transistors in Ultra-Low Power Analog Design. VLSI-SoC (Selected Papers) Matthieu Couriol, Patsy Cadareanu, Edouard Giacomin, Pierre-Emmanuel Gaillardon
2021	C	`conf`	A Novel High-Gain Amplifier Circuit Using Super-Steep-Subthreshold-Slope Field-Effect Transistors. VLSI-SoC Matthieu Couriol, Patsy Cadareanu, Edouard Giacomin, Pierre-Emmanuel Gaillardon
2021	C	`conf`	Area-Efficient Multiplier Designs Using a 3D Nanofabric Process Flow. ISCAS Edouard Giacomin, Francky Catthoor, Pierre-Emmanuel Gaillardon
2021	C	`conf`	Smart-Redundancy: An Alternative SEU/SET Mitigation Method for FPGAs. ISCAS Aurélien Alacchi, Edouard Giacomin, Xifan Tang, Pierre-Emmanuel Gaillardon
2020	—	`conf`	3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic Designs. VLSI-SoC (Selected Papers) Edouard Giacomin, Jürgen Bömmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon
2020	A	`conf`	A RRAM-based FPGA for Energy-efficient Edge Computing. DATE Xifan Tang, Edouard Giacomin, Patsy Cadareanu, Ganesh Gore, Pierre-Emmanuel Gaillardon
2020	C	`conf`	Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric Process Flow. VLSI-SOC Edouard Giacomin, Jürgen Bömmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon
2020	J	`jnl`	OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs. IEEE Micro Xifan Tang, Edouard Giacomin, Baudouin Chauviere, Aurélien Alacchi, Pierre-Emmanuel Gaillardon
2020	A*	`conf`	SpinalFlow: An Architecture and Dataflow Tailored for Spiking Neural Networks. ISCA Surya Narayanan, Karl Taht, Rajeev Balasubramonian, Edouard Giacomin, Pierre-Emmanuel Gaillardon
2019	—	`conf`	A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors. VLSI-SoC (Selected Papers) Patsy Cadareanu, Ganesh Gore, Edouard Giacomin, Pierre-Emmanuel Gaillardon
2019	C	`conf`	A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors. VLSI-SoC Ganesh Gore, Patsy Cadareanu, Edouard Giacomin, Pierre-Emmanuel Gaillardon
2019	C	`conf`	A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories. VLSI-SoC João Vieira, Edouard Giacomin, Yasir Mahmood Qureshi, Marina Zapater, Xifan Tang, Shahar Kvatinsky, David Atienza, Pierre-Emmanuel Gaillardon
2019	J	`jnl`	A Robust Digital RRAM-Based Convolutional Block for Low-Power Image Processing and Learning Applications. IEEE Trans. Circuits Syst. I Regul. Pap. Edouard Giacomin, Tzofnat Greenberg-Toledo, Shahar Kvatinsky, Pierre-Emmanuel Gaillardon
2019	—	`conf`	A Study on Switch Block Patterns for Tileable FPGA Routing Architectures. FPT Xifan Tang, Edouard Giacomin, Aurélien Alacchi, Pierre-Emmanuel Gaillardon
2019	—	`conf`	Accelerating Inference on Binary Neural Networks with Digital RRAM Processing. VLSI-SoC (Selected Papers) João Vieira, Edouard Giacomin, Yasir Mahmood Qureshi, Marina Zapater, Xifan Tang, Shahar Kvatinsky, David Atienza, Pierre-Emmanuel Gaillardon
2019	J	`jnl`	FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. Xifan Tang, Edouard Giacomin, Giovanni De Micheli, Pierre-Emmanuel Gaillardon
2019	A*	`conf`	GenCache: Leveraging In-Cache Operators for Efficient Sequence Alignment. MICRO Anirban Nag, C. N. Ramachandra, Rajeev Balasubramonian, Ryan Stutsman, Edouard Giacomin, Hari Kambalasubramanyam, Pierre-Emmanuel Gaillardon
2019	B	`conf`	OpenFPGA: An Opensource Framework Enabling Rapid Prototyping of Customizable FPGAs. FPL Xifan Tang, Edouard Giacomin, Aurélien Alacchi, Baudouin Chauviere, Pierre-Emmanuel Gaillardon
2019	A*	`conf`	Wire-Aware Architecture and Dataflow for CNN Accelerators. MICRO Sumanth Gudaparthi, Surya Narayanan, Rajeev Balasubramonian, Edouard Giacomin, Hari Kambalasubramanyam, Pierre-Emmanuel Gaillardon
2018	C	`conf`	Differential Power Analysis Mitigation Technique Using Three-Independent-Gate Field Effect Transistors. VLSI-SoC Edouard Giacomin, Pierre-Emmanuel Gaillardon
2018	J	`jnl`	Post-P&R Performance and Power Analysis for RRAM-Based FPGAs. IEEE J. Emerg. Sel. Topics Circuits Syst. Xifan Tang, Edouard Giacomin, Giovanni De Micheli, Pierre-Emmanuel Gaillardon
2017	J	`jnl`	Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(RAM) Programming Structure. IEEE Trans. Circuits Syst. I Regul. Pap. Xifan Tang, Edouard Giacomin, Giovanni De Micheli, Pierre-Emmanuel Gaillardon
2017	—	`conf`	Low-power multiplexer designs using three-independent-gate field effect transistors. NANOARCH Edouard Giacomin, Jorge Romero Gonzalez, Pierre-Emmanuel Gaillardon
2017	—	`conf`	Physical Design Considerations of One-level RRAM-based Routing Multiplexers. ISPD Xifan Tang, Edouard Giacomin, Giovanni De Micheli, Pierre-Emmanuel Gaillardon