Edoardo Fusella

21 papers A 3B 2Journal 11Unranked 5
YearRankTypeTitle / Venue / Authors
2019 J jnl
Guest Editors' Introduction: Emerging Networks-on-Chip Designs, Technologies, and Applications.
ACM J. Emerg. Technol. Comput. Syst.
Edoardo Fusella, Mahdi Nikdast, Ian O'Connor, José Flich, Sudeep Pasricha
2018 J jnl
Exploring manycore architectures for next-generation HPC systems through the MANGO approach.
Microprocess. Microsystems
José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Etienne Cappe, Alessandro Cilardo, Leon Dragic, Alexandre Dray, Alen Duspara, William Fornaciari, Edoardo Fusella, Mirko Gagliardi, Gerald Guillaume, Daniel Hofman, Ynse Hoornenborg, Arman Iranfar, Mario Kovac, Davide Zoni
2018 — conf
Improving Deep Learning with a customizable GPU-like FPGA-based accelerator.
PRIME
Mirko Gagliardi, Edoardo Fusella, Alessandro Cilardo
2018 J jnl
Lattice-Based Turn Model for Adaptive Routing.
IEEE Trans. Parallel Distributed Syst.
Edoardo Fusella, Alessandro Cilardo
2018 J jnl
Reducing Power Consumption of Lasers in Photonic NoCs through Application-Specific Mapping.
ACM J. Emerg. Technol. Comput. Syst.
Edoardo Fusella, Alessandro Cilardo
2018 A conf
Understanding turn models for adaptive routing: The modular approach.
DATE
Edoardo Fusella, Alessandro Cilardo
2017 — conf
A Deterministic Approach to Improve Inter-Domain Parallelism of Clustered MPSoC Interconnects.
AINA Workshops
Edoardo Fusella
2017 — conf
Deeply Heterogeneous Many-Accelerator Infrastructure for HPC Architecture Exploration.
PARCO
José Flich, Alessandro Cilardo, Mario Kovaç, Rafael Tornero, Mirko Gagliardi, Edoardo Fusella, José Maria Martínez, Tomás Picornell
2017 J jnl
H
IEEE Trans. Very Large Scale Integr. Syst.
Edoardo Fusella, Alessandro Cilardo
2017 J jnl
Path Setup for Hybrid NoC Architectures Exploiting Flooding and Standby.
IEEE Trans. Parallel Distributed Syst.
Edoardo Fusella, José Flich, Alessandro Cilardo
2016 J jnl
Crosstalk-Aware Automated Mapping for Optical Networks-on-Chip.
ACM Trans. Embed. Comput. Syst.
Edoardo Fusella, Alessandro Cilardo
2016 J jnl
Design automation for application-specific on-chip interconnects: A survey.
Integr.
Alessandro Cilardo, Edoardo Fusella
2016 J jnl
Minimizing power loss in optical networks-on-chip through application-specific mapping.
Microprocess. Microsystems
Edoardo Fusella, Alessandro Cilardo
2016 A conf
PhoNoCMap: An application mapping tool for photonic networks-on-chip.
DATE
Edoardo Fusella, Alessandro Cilardo
2015 — conf
Crosstalk-Aware Mapping for Tile-Based Optical Network-on-Chip.
HPCC/CSS/ICESS
Edoardo Fusella, Alessandro Cilardo
2015 J jnl
Exploiting Concurrency for the Automated Synthesis of MPSoC Interconnects.
ACM Trans. Embed. Comput. Syst.
Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo
2015 — conf
On the Design of a Path-Setup Architecture for Exploiting Hybrid Photonic-Electronic NoCs.
SiPhotonics@HiPEAC
Edoardo Fusella, José Flich, Alessandro Cilardo, Antonino Mazzeo
2015 B conf
Scheduling-aware interconnect synthesis for FPGA-based Multi-Processor Systems-on-Chip.
FPL
Edoardo Fusella, Alessandro Cilardo, Antonino Mazzeo
2014 J jnl
Automated design space exploration for FPGA-based heterogeneous interconnects.
Des. Autom. Embed. Syst.
Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo, Nicola Mazzocca
2014 A conf
Joint communication scheduling and interconnect synthesis for FPGA-based many-core systems.
DATE
Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo
2013 B conf
Automated synthesis of FPGA-based heterogeneous interconnect topologies.
FPL
Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo