Edith Beigné - RankMe

106 papers A* 4A 5B 2C 8Journal 27Unranked 60

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	A 3D Design Methodology for Integrated Wearable SoCs: Enabling Energy Efficiency and Enhanced Performance at Iso-Area Footprint. DATE Huseyin Ekin Sumbul, Arne Symons, Lita Yang, Huichu Liu, Tony F. Wu, Matheus Trevisan Moreira, Debabrata Mohapatra, Abhinav Agarwal, Kaushik Ravindran, Chris Thompson, Yuecheng Li, Edith Beigné
2025	A*	`conf`	LLMs: A Driving Force in Next Generation Digital Design Automation. DAC Matheus T. Moreira, Aram H. Markosyan, Chris Cummins, Warren Hunt, Gabriel Synnaeve, Edith Beigné
2024	—	`conf`	11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint. ISSCC Tony F. Wu, Huichu Liu, Huseyin Ekin Sumbul, Lita Yang, Dipti Baheti, Jeremy Coriell, William Koven, Anu Krishnan, Mohit Mittal, Matheus Trevisan Moreira, Max Waugaman, Laurent Ye, Edith Beigné
2024	J	`jnl`	A Fully Digital and Row-Pipelined Compute-in-Memory Neural Network Accelerator With System-on-Chip-Level Benchmarking for Augmented/Virtual Reality Applications. IEEE Micro Huseyin Ekin Sumbul, Jae-sun Seo, Daniel H. Morris, Edith Beigné
2024	—	`conf`	Characterization and Design of 3D-Stacked Memory for Image Signal Processing on AR/VR Devices. MEMSYS Lita Yang, Changjung Kao, Sriseshan Srikanth, Huseyin Ekin Sumbul, Tony F. Wu, Huichu Liu, Edith Beigné
2023	—	`conf`	A QDI Interconnect for 3D Systems Using Industry Standard EDA and Cell Libraries. ASYNC Matheus Trevisan Moreira, William Koven, Tony F. Wu, Huseyin Ekin Sumbul, Edith Beigné
2023	—	`conf`	A prototype 5nm custom sensor SoC for Augmented Reality/Virtual Reality targeting Smartglasses with embedded computer vision, audio, security and ML. VLSI Technology and Circuits Karl Kaiser, Dinesh Patil, Edith Beigné
2022	A	`conf`	A Uniform Latency Model for DNN Accelerators with Diverse Architectures and Dataflows. DATE Linyan Mei, Huichu Liu, Tony F. Wu, Huseyin Ekin Sumbul, Marian Verhelst, Edith Beigné
2022	—	`conf`	Co-Optimization of SRAM Circuits with Sequential Access Patterns in a 7nm SoC Achieving 58% Memory Energy Reduction for AR Applications. VLSI Technology and Circuits Daniel H. Morris, Huichu Liu, Tony F. Wu, Huseyin Ekin Sumbul, Elnaz Ansari, Alexandre Barachant, Jonathan Reid, Edith Beigné
2022	—	`conf`	System-Level Design and Integration of a Prototype AR/VR Hardware Featuring a Custom Low-Power DNN Accelerator Chip in 7nm Technology for Codec Avatars. CICC Huseyin Ekin Sumbul, Tony F. Wu, Yuecheng Li, Syed Shakib Sarwar, William Koven, Eli Murphy-Trotzky, Xingxing Cai, Elnaz Ansari, Daniel H. Morris, Huichu Liu, Doyun Kim, Edith Beigné
2022	J	`jnl`	Three-Dimensional Stacked Neural Network Accelerator Architectures for AR/VR Applications. IEEE Micro Lita Yang, Robert M. Radway, Yu-Hsin Chen, Tony F. Wu, Huichu Liu, Elnaz Ansari, Vikas Chandra, Subhasish Mitra, Edith Beigné
2021	—	`conf`	Evaluation of Low-Voltage SRAM for Error-Resilient Augmented Reality Applications. SiPS Tony F. Wu, Doyun Kim, Daniel H. Morris, Edith Beigné
2020	—	`conf`	SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15, 000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency. VLSI Circuits Ivan Miro Panades, Benoît Tain, Jean-Frédéric Christmann, David Coriat, Romain Lemaire, Clement Jany, Baudouin Martineau, Fabrice Chaix, Anthony Quelen, Emmanuel Pluchart, Jean-Philippe Noel, Reda Boumchedda, Adam Makosiej, Maxime Montoya, Simone Bacles-Min, David Briand, Jean-Marc Philippe, Alexandre Valentian, Frédéric Heitzmann, Edith Beigné, Fabien Clermidy
2020	J	`jnl`	Spiking Neural Networks Hardware Implementations and Challenges: a Survey. CoRR Maxence Bouvier, Alexandre Valentian, Thomas Mesquida, François Rummens, Marina Reyboz, Elisa Vianello, Edith Beigné
2019	—	`conf`	A 2048-Neuron Spiking Neural Network Accelerator With Neuro-Inspired Pruning And Asynchronous Network On Chip In 40nm CMOS. CICC Sung-Gun Cho, Edith Beigné, Zhengya Zhang
2019	—	`conf`	A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques. ISSCC Tony F. Wu, Binh Q. Le, Robert M. Radway, Andrew Bartolo, William Hwang, Seungbin Jeong, Haitong Li, Pulkit Tandon, Elisa Vianello, Pascal Vivet, Etienne Nowak, Mary Wootters, H.-S. Philip Wong, Mohamed M. Sabry Aly, Edith Beigné, Subhasish Mitra
2019	J	`jnl`	A 5500-frames/s 85-GOPS/W 3-D Stacked BSI Vision Chip Based on Parallel In-Focal-Plane Acquisition and Processing. IEEE J. Solid State Circuits Laurent Millet, Stéphane Chevobbe, Caaliph Andriamisaina, Lamine Benaissa, Edouard Deschaseaux, Edith Beigné, Karim Ben Chehida, Maria Lepecq, Mehdi Darouich, Fabrice Guellec, Thomas Dombek, Marc Duranton
2019	J	`jnl`	Fine-Grain Back Biasing for the Design of Energy-Quality Scalable Operators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Daniele Jahier Pagliari, Yves Durand, David Coriat, Edith Beigné, Enrico Macii, Massimo Poncino
2019	C	`conf`	Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture. VLSI-SoC Roman Gauchi, Maha Kooli, Pascal Vivet, Jean-Philippe Noël, Edith Beigné, Subhasish Mitra, Henri-Pierre Charles
2019	—	`conf`	Misalignment Analysis and Electrical Performance of High Density 3D-IC interconnects. 3DIC Imed Jani, Didier Lattard, Pascal Vivet, Lucile Arnaud, Edith Beigné
2019	J	`jnl`	Spiking Neural Networks Hardware Implementations and Challenges: A Survey. ACM J. Emerg. Technol. Comput. Syst. Maxence Bouvier, Alexandre Valentian, Thomas Mesquida, François Rummens, Marina Reyboz, Elisa Vianello, Edith Beigné
2019	B	`conf`	Test Solutions for High Density 3D-IC Interconnects - Focus on SRAM-on-Logic Partitioning. ETS Imed Jani, Didier Lattard, Pascal Vivet, Jean Durupt, Sébastien Thuries, Edith Beigné
2018	—	`conf`	A 2.5μW 0.0067mm ISSCC Anthony Quelen, Gaël Pillonnet, Philippe Flatresse, Edith Beigné
2018	—	`conf`	A 5500FPS 85GOPS/W 3D Stacked BSI Vision Chip Based on Parallel in-Focal-Plane Acquisition and Processing. VLSI Circuits Laurent Millet, Stéphane Chevobbe, Caaliph Andriamisaina, Edith Beigné, Fabrice Guellec, Thomas Dombek, Lamine Benaissa, Edouard Deschaseaux, Marc Duranton, K. Benchehida, Mehdi Darouich, Maria Lepecq
2018	B	`conf`	BISTs for post-bond test and electrical analysis of high density 3D interconnect defects. ETS Imed Jani, Didier Lattard, Pascal Vivet, Lucile Arnaud, Edith Beigné
2018	—	`conf`	Benefits of Joint Optimization of Tunable Wake-up Radio Architecture and Protocols. ICECS Mickael Maman, Dominique Morche, Baudouin Martineau, Clement Jany, Ivan Miro Panades, Anthony Quelen, Franck Badets, Edith Beigné
2018	—	`conf`	Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCubeTM Technology. NANOARCH Reda Boumchedda, Jean-Philippe Noel, Bastien Giraud, Adam Makosiej, Marco Antonio Rios, Eduardo Esmanhotto, Emilien Bourde-Cicé, Mathis Bellet, David Turgis, Edith Beigné
2018	—	`conf`	FDSOI Circuit Design for High Energy Efficiency: Wide Operating Range and ULP Applications - a 7-Year Experience. ESSCIRC Edith Beigné
2018	—	`conf`	FDSOI circuit design for high energy efficiency: Wide operating range and ULP applications - a 7-year experience. ESSDERC Edith Beigné
2018	—	`conf`	Monolithic 3D: an alternative to advanced CMOS scaling, technology perspectives and associated design methodology challenges. ICECS Pascal Vivet, Sébastien Thuries, Olivier Billoint, Sylvain Choisnet, Didier Lattard, Edith Beigné, Perrine Batude
2018	—	`conf`	Session 18 overview: Adaptive circuits and digital regulators: Digital circuit techniques subcommittee. ISSCC Dennis Sylvester, Koji Hirairi, Edith Beigné
2018	—	`conf`	Session 7 overview: Neuromorphic, clocking and security circuits: Digital circuits subcommittee. ISSCC Youngmin Shin, Phillip J. Restle, Edith Beigné
2018	C	`conf`	Some Local Stability Properties of an Autonomous Long Short-Term Memory Neural Network Model. ISCAS Dusan M. Stipanovic, Boris Murmann, Matteo Causo, Aleksandra Lekic, Vicenc Rubies-Royo, Claire J. Tomlin, Edith Beigné, Sébastien Thuries, Mykhailo Zarudniev, Suzanne Lesecq
2017	—	`conf`	A 128x128, 34μm pitch, 8.9mW, 190mK NETD, TECless Uncooled IR bolometer image sensor with column-wise processing. IMSE Laurent Alacoque, Sébastien Martin, Wilfried Rabaud, Edith Beigné, Antoine Dupret, Bertrand Dupont
2017	J	`jnl`	A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Anuj Grover, G. S. Visweswaran, Chittoor R. Parthasarathy, Mohammad Daud, David Turgis, Bastien Giraud, Jean-Philippe Noel, Ivan Miro Panades, Guillaume Moritz, Edith Beigné, Philippe Flatresse, Promod Kumar, Shamsi Azmi
2017	J	`jnl`	A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links. IEEE J. Solid State Circuits Pascal Vivet, Yvain Thonnart, Romain Lemaire, Cristiano Santos, Edith Beigné, Christian Bernard, Florian Darve, Didier Lattard, Ivan Miro Panades, Denis Dutoit, Fabien Clermidy, Séverine Cheramy, Abbas Sheibanyrad, Frédéric Pétrot, Eric Flamand, Jean Michailos, Alexandre Arriordaz, Lee Wang, Juergen Schloeffel
2017	A	`conf`	A methodology for the design of dynamic accuracy operators by runtime back bias. DATE Daniele Jahier Pagliari, Yves Durand, David Coriat, Anca Molnos, Edith Beigné, Enrico Macii, Massimo Poncino
2017	J	`jnl`	AES Datapath Optimization Strategies for Low-Power Low-Energy Multisecurity-Level Internet-of-Things Applications. IEEE Trans. Very Large Scale Integr. Syst. Duy-Hieu Bui, Diego Puschini, Simone Bacles-Min, Edith Beigné, Xuan-Tu Tran
2017	J	`jnl`	Adaptive Architectures, Circuits and Technology Solutions for Future IoT Systems. J. Low Power Electron. Marc Belleville, Anca Molnos, Gilles Sicard, Jean-Frédéric Christmann, Dominique Morche, Duy-Hieu Bui, Diego Puschini, Suzanne Lesecq, Edith Beigné
2017	—	`conf`	Architecture exploration of a fixed point computation unit using precise timing spiking neurons. PATMOS Thomas Mesquida, Alexandre Valentian, David Bol, Edith Beigné
2017	J	`jnl`	Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster. IEEE Micro Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Philippe Flatresse, Luca Benini
2017	J	`jnl`	High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques. IEEE Trans. Very Large Scale Integr. Syst. Reda Boumchedda, Jean-Philippe Noel, Bastien Giraud, Kaya Can Akyel, Melanie Brocard, David Turgis, Edith Beigné
2017	C	`conf`	In-situ Fmax/Vmin tracking for energy efficiency and reliability optimization. IOLTS Ivan Miro Panades, Edith Beigné, Olivier Billoint, Yvain Thonnart
2017	—	`conf`	Innovative structures to test bonding alignment and characterize high density interconnects in 3D-IC. NEWCAS Imed Jani, Didier Lattard, Pascal Vivet, Edith Beigné
2017	—	`conf`	Session 20 overview: Digital voltage regulators and low-power techniques. ISSCC Atsuki Inoue, Dennis Sylvester, Edith Beigné
2017	—	`conf`	Session 26 overview: Processor-power management and clocking. ISSCC Kathy Wilcox, Youngmin Shin, Edith Beigné
2017	—	`conf`	Session 8 overview: Digital PLLs and security circuits. ISSCC Yasuhisa Shimazaki, John Maneatis, Edith Beigné
2016	—	`conf`	193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. COOL Chips Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Fady Abouzeid, Philippe Flatresse, Luca Benini
2016	—	`conf`	8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links. ISSCC Pascal Vivet, Yvain Thonnart, Romain Lemaire, Edith Beigné, Christian Bernard, Florian Darve, Didier Lattard, Ivan Miro Panades, Cristiano Santos, Fabien Clermidy, Séverine Cheramy, Frédéric Pétrot, Eric Flamand, Jean Michailos
2016	J	`jnl`	Introduction to the January Special Issue on the 2015 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits Edith Beigné, Jinuk Luke Shin, Yusuke Oike, Chulwoo Kim, Jan Genoe
2016	—	`conf`	Three-Independent-Gate Transistors: Opportunities in digital, analog and RF applications. LATS Pierre-Emmanuel Gaillardon, Romain Magni, Luca Gaetano Amarù, Mehdi Hasan, Ross Walker, Berardi Sensale Rodriguez, Jean-Frédéric Christmann, Edith Beigné
2016	—	`conf`	Tracking BTI and HCI effects at circuit-level in adaptive systems. NEWCAS Maurício Altieri, Suzanne Lesecq, Edith Beigné, Olivier Héron, Diego Puschini
2016	—	`conf`	Ultra low-power and low-energy 32-bit datapath AES architecture for IoT applications. ICICDT Duy-Hieu Bui, Diego Puschini, Simone Bacles-Min, Edith Beigné, Xuan-Tu Tran
2015	J	`jnl`	A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking. IEEE J. Solid State Circuits Edith Beigné, Alexandre Valentian, Ivan Miro Panades, Robin Wilson, Philippe Flatresse, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Jean-Philippe Noel, Olivier Thomas, Yvain Thonnart
2015	J	`jnl`	A Survey on Low-Power Techniques with Emerging Technologies: From Devices to Systems. ACM J. Emerg. Technol. Comput. Syst. Pierre-Emmanuel Gaillardon, Edith Beigné, Suzanne Lesecq, Giovanni De Micheli
2015	—	`conf`	Dedicated network for distributed configuration in a mixed-signal Wireless Sensor Node circuit. PATMOS Soundous Chairat, Edith Beigné, Marc Belleville
2015	—	`conf`	Evaluation and mitigation of aging effects on a digital on-chip voltage and temperature sensor. PATMOS Maurício Altieri, Suzanne Lesecq, Diego Puschini, Olivier Héron, Edith Beigné, Jorge Rodas
2015	C	`conf`	Fine-grain DVFS and AVFS techniques for complex SoC design: An overview of architectural solutions through technology nodes. ISCAS Edith Beigné, Fabien Clermidy, Didier Lattard, Ivan Miro Panades, Yvain Thonnart, Pascal Vivet
2015	—	`conf`	Non-volatility for Ultra-Low Power Asynchronous Circuits in Hybrid CMOS/Magnetic Technology. ASYNC Eldar Zianbetov, Edith Beigné, Gregory di Pendina
2015	—	`conf`	Power gain estimation of an event-driven wake-up controller dedicated to WSN's microcontroller. NEWCAS Florent Berthier, Edith Beigné, Pascal Vivet, Olivier Sentieys
2015	—	`conf`	Radiative Effects on MRAM-Based Non-Volatile Elementary Structures. ISVLSI Jeremy Lopes, Gregory di Pendina, Eldar Zianbetov, Edith Beigné, Lionel Torres
2015	—	`conf`	UTBB FDSOI technology flexibility for ultra low power internet-of-things applications. ESSDERC Edith Beigné, Jean-Frédéric Christmann, Alexandre Valentian, Olivier Billoint, Esteve Amat, Dominique Morche
2015	—	`conf`	Ultra-low power volatile and non-volatile asynchronous circuits using back-biasing. ECCTD Edith Beigné, Jean-Frédéric Christmann, Eldar Zianbetov, Gregory di Pendina
2015	—	`conf`	Unified Power Format (UPF) methodology in a vendor independent flow. PATMOS Emilie Garat, David Coriat, Edith Beigné, Leandro Stefanazzi
2014	—	`conf`	27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking. ISSCC Robin Wilson, Edith Beigné, Philippe Flatresse, Alexandre Valentian, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Ivan Miro Panades, Jean-Philippe Noël, Bertrand Pelloux-Prayer, Philippe Roche, Olivier Thomas, Yvain Thonnart, David Turgis, Fabien Clermidy, Philippe Magarshack
2014	J	`jnl`	A Fine-Grain Variation-Aware Dynamic Vdd-Hopping AVFS Architecture on a 32 nm GALS MPSoC. IEEE J. Solid State Circuits Ivan Miro Panades, Edith Beigné, Yvain Thonnart, Laurent Alacoque, Pascal Vivet, Suzanne Lesecq, Diego Puschini, Anca Molnos, Farhat Thabet, Benoît Tain, Karim Ben Chehida, Sylvain Engels, Robin Wilson, Didier Fuin
2014	J	`jnl`	Dynamic Variability Monitoring Using Statistical Tests for Energy Efficient Adaptive Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. Lionel Vincent, Edith Beigné, Suzanne Lesecq, Julien Mottin, David Coriat, Philippe Maurine
2014	C	`conf`	FIFO-level-based power management and its application to an H.264 encoder. IECON Ngoc-Mai Nguyen, Warody Lombardi, Edith Beigné, Suzanne Lesecq, Xuan-Tu Tran
2014	—	`conf`	H.264/AVC hardware encoders and low-power features. APCCAS Ngoc-Mai Nguyen, Edith Beigné, Suzanne Lesecq, Duy-Hieu Bui, Nam-Khanh Dang, Xuan-Tu Tran
2014	A*	`conf`	Power management through DVFS and dynamic body biasing in FD-SOI circuits. DAC Yeter Akgul, Diego Puschini, Suzanne Lesecq, Edith Beigné, Ivan Miro Panades, Pascal Benoit, Lionel Torres
2013	—	`conf`	A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC. ESSCIRC Edith Beigné, Ivan Miro-Panades, Yvain Thonnart, Laurent Alacoque, Pascal Vivet, Suzanne Lesecq, Diego Puschini, Farhat Thabet, Benoît Tain, K. Benchehida, Sylvain Engels, Robin Wilson, Didier Fuin
2013	A	`conf`	A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits. DATE Smriti Joshi, Anne Lombardot, Marc Belleville, Edith Beigné, Stéphane Girard
2013	—	`conf`	Automatic Leakage Control for Wide Range Performance QDI Asynchronous Circuits in FD-SOI Technology. ASYNC Jérémie Hamon, Edith Beigné
2013	C	`conf`	Event-based DVFS control in GALS-ANoC MPSoCs. ACC Sylvain Durand, Suzanne Lesecq, Edith Beigné, Diego Puschini
2013	C	`conf`	Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology. VLSI-SoC Bertrand Pelloux-Prayer, Alexandre Valentian, Bastien Giraud, Yvain Thonnart, Jean-Philippe Noel, Philippe Flatresse, Edith Beigné
2013	—	`conf`	Methodology for Power Mode selection in FD-SOI circuits with DVFS and Dynamic Body Biasing. PATMOS Yeter Akgul, Diego Puschini, Suzanne Lesecq, Edith Beigné, Pascal Benoit, Lionel Torres
2013	A	`conf`	Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs. DATE Edith Beigné, Alexandre Valentian, Bastien Giraud, Olivier Thomas, Thomas Benoist, Yvain Thonnart, Serge Bernard, Guillaume Moritz, Olivier Billoint, Y. Maneglia, Philippe Flatresse, Jean-Philippe Noel, Fady Abouzeid, Bertrand Pelloux-Prayer, Anuj Grover, Sylvain Clerc, Philippe Roche, Julien Le Coz, Sylvain Engels, Robin Wilson
2012	—	`conf`	A Pseudo-Synchronous Implementation Flow for WCHB QDI Asynchronous Circuits. ASYNC Yvain Thonnart, Edith Beigné, Pascal Vivet
2012	A*	`conf`	Embedding statistical tests for on-chip dynamic voltage and temperature monitoring. DAC Lionel Vincent, Philippe Maurine, Suzanne Lesecq, Edith Beigné
2012	A*	`conf`	Energy harvesting and power management for autonomous sensor nodes. DAC Jean-Frédéric Christmann, Edith Beigné, Cyril Condemine, Jérôme Willemin, Christian Piguet
2012	—	`conf`	Event-driven asynchronous voltage monitoring in energy harvesting platforms. NEWCAS Jean-Frédéric Christmann, Edith Beigné, Cyril Condemine, Christian Piguet
2012	C	`conf`	Local Condition Monitoring in integrated circuits using a set of Kolmogorov-Smirnov tests. CCA Lionel Vincent, Suzanne Lesecq, Philippe Maurine, Edith Beigné
2012	J	`jnl`	Statistical Estimation of Dominant Physical Parameters for Leakage Variability in 32 Nanometer CMOS, Under Supply Voltage Variations. J. Low Power Electron. Smriti Joshi, Anne Lombardot, Philippe Flatresse, Carmelo D'Agostino, Andre Juge, Edith Beigné, Stéphane Girard
2011	J	`jnl`	Architecture and Robust Control of a Digital Frequency-Locked Loop for Fine-Grain Dynamic Voltage and Frequency Scaling in Globally Asynchronous Locally Synchronous Structures. J. Low Power Electron. Carolina Albea, Diego Puschini, Pascal Vivet, Ivan Miro Panades, Edith Beigné, Suzanne Lesecq
2011	J	`jnl`	Bringing Robustness and Power Efficiency to Autonomous Energy-Harvesting Microsystems. IEEE Des. Test Comput. Jean-Frédéric Christmann, Edith Beigné, Cyril Condemine, Pascal Vivet, Jérôme Willemin, Nicolas Leblond, Christian Piguet
2011	—	`conf`	Low-Cost Dynamic Voltage and Frequency Management Based upon Robust Control Techniques under Thermal Constraints. FMCO Sylvain Durand, Suzanne Lesecq, Edith Beigné, Christian Fabre, Lionel Vincent, Diego Puschini
2011	J	`jnl`	On-line Power Optimization of Data Flow Multi-Core Architecture Based on Vdd-Hopping for Local Dynamic Voltage and Frequency Scaling. J. Low Power Electron. Pascal Vivet, Edith Beigné, Hugo Lebreton, Nacer-Eddine Zergainoh
2011	J	`jnl`	Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization. Microelectron. J. Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, Michel Robert, Philippe Maurine, Nadine Azémard
2010	J	`jnl`	An On-Chip Multi-Mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-Power Domain SoC Using a 65-nm Standard CMOS Logic Process. J. Low Power Electron. Motoi Ichihashi, Hélène Lhermet, Edith Beigné, Frédéric Rothan, Marc Belleville, Amara Amara
2010	—	`conf`	Bringing Robustness and Power Efficiency to Autonomous Energy Harvesting Microsystems. ASYNC Jean-Frédéric Christmann, Edith Beigné, Cyril Condemine, Nicolas Leblond, Pascal Vivet, G. Waltisperger, Jérôme Willemin
2010	—	`conf`	On Line Power Optimization of Data Flow Multi-core Architecture Based on Vdd-Hopping for Local DVFS. PATMOS Pascal Vivet, Edith Beigné, Hugo Lebreton, Nacer-Eddine Zergainoh
2009	J	`jnl`	An Asynchronous Power Aware and Adaptive NoC Based Circuit. IEEE J. Solid State Circuits Edith Beigné, Fabien Clermidy, Hélène Lhermet, Sylvain Miermont, Yvain Thonnart, Xuan-Tu Tran, Alexandre Valentian, Didier Varreau, Pascal Vivet, Xavier Popon, Hugo Lebreton
2009	—	`conf`	An On-Chip Multi-mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-power Domain SoC Using a 65-nm Standard CMOS Logic Process. PATMOS Motoi Ichihashi, Hélène Lhermet, Edith Beigné, Frédéric Rothan, Marc Belleville, Amara Amara
2009	—	`conf`	Design and Implementation of a GALS Adapter for ANoC Based Architectures. ASYNC Yvain Thonnart, Edith Beigné, Pascal Vivet
2009	—	`conf`	Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities. PATMOS Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, Michel Robert, Philippe Maurine, Nadine Azémard
2009	J	`jnl`	Power Reduction of Asynchronous Logic Circuits Using Activity Detection. IEEE Trans. Very Large Scale Integr. Syst. Yvain Thonnart, Edith Beigné, Alexandre Valentian, Pascal Vivet
2008	J	`jnl`	A Reconfigurable Baseband Platform Based on an Asynchronous Network-on-Chip. IEEE J. Solid State Circuits Didier Lattard, Edith Beigné, Fabien Clermidy, Yves Durand, Romain Lemaire, Pascal Vivet, Friedbert Berens
2008	—	`conf`	A fully integrated power supply unit for fine grain power management application to embedded Low Voltage SRAMs. ESSCIRC Edith Beigné, Fabien Clermidy, Sylvain Miermont, Alexandre Valentian, Pascal Vivet, S. Barasinski, F. Blisson, N. Kohli, S. Kumar
2008	J	`jnl`	Automatic Gate Biasing of an SCCMOS Power Switch Achieving Maximum Leakage Reduction and Lowering Leakage Current Variability. IEEE J. Solid State Circuits Alexandre Valentian, Edith Beigné
2008	—	`conf`	Automatic Power Regulation Based on an Asynchronous Activity Detection and its Application to ANOC Node Leakage Reduction. ASYNC Yvain Thonnart, Edith Beigné, Alexandre Valentian, Pascal Vivet
2008	—	`conf`	Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC. NOCS Edith Beigné, Fabien Clermidy, Sylvain Miermont, Pascal Vivet
2007	—	`conf`	A Telecom Baseband Circuit based on an Asynchronous Network-on-Chip. ISSCC Didier Lattard, Edith Beigné, Christian Bernard, Catherine Bour, Fabien Clermidy, Yves Durand, Jean Durupt, Didier Varreau, Pascal Vivet, Pierre Penard, Arnaud Bouttier, Friedbert Berens
2007	—	`conf`	Gate bias circuit for an SCCMOS power switch achieving maximum leakage reduction. ESSCIRC Alexandre Valentian, Edith Beigné
2006	—	`conf`	AsyncRFID: Fully Asynchronous Contactless Systems, Providing High Data Rates, Low Power and Dynamic Adaptation. ASYNC D. Caucheteux, Edith Beigné, Elisabeth Crochon, Marc Renaudin
2006	—	`conf`	Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture. ASYNC Edith Beigné, Pascal Vivet
2005	—	`conf`	An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework. ASYNC Edith Beigné, Fabien Clermidy, Pascal Vivet, Alain Clouard, Marc Renaudin