Edgar Sánchez-Sinencio

249 papers A* 1A 7C 19Misc 4Journal 150Unranked 67
YearRankTypeTitle / Venue / Authors
2022 J jnl
Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction.
IEEE Trans. Emerg. Top. Comput.
Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran
2021 J jnl
A CMOS Energy Harvesting Interface Circuit With Cycle-to-Cycle Frequency-to-Amplitude Conversion MPPT for Centimeter-Scale Wind Turbine.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zizhen Zeng, Johan J. Estrada-López, Bo Wang, Edgar Sánchez-Sinencio
2021 J jnl
Analog/RF IP Protection: Attack Models, Defense Techniques, and Challenges.
IEEE Trans. Circuits Syst. II Express Briefs
Adriana C. Sanabria-Borbon, Nithyashankari Gummidipoondi Jayasankaran, Jiang Hu, Jeyavijayan Rajendran, Edgar Sánchez-Sinencio
2021 J jnl
Current Reference Circuits: A Tutorial.
IEEE Trans. Circuits Syst. II Express Briefs
Sanghoon Lee, Edgar Sánchez-Sinencio
2021 J jnl
Synthesis of High-Order Continuously Tunable Low-Pass Active-R Filters.
IEEE Trans. Circuits Syst. I Regul. Pap.
Adriana C. Sanabria-Borbon, Edgar Sánchez-Sinencio
2020 J jnl
A 0.6-V Power-Efficient Active-RC Analog Low-Pass Filter With Cutoff Frequency Selection.
IEEE Trans. Very Large Scale Integr. Syst.
Fernando Lavalle-Aviles, Edgar Sánchez-Sinencio
2020 J jnl
A 1-nA 4.5-nW 289-ppm/°C Current Reference Using Automatic Calibration.
IEEE J. Solid State Circuits
Sanghoon Lee, Stephen K. Heinrich-Barna, Kyoohyun Noh, Keith Kunz, Edgar Sánchez-Sinencio
2020 J jnl
A 175.2-mW 4-Stage OTA With Wide Load Range (400 pF-12 nF) Using Active Parallel Compensation.
IEEE Trans. Very Large Scale Integr. Syst.
Samuel Annor Fordjour, Joseph Riad, Edgar Sánchez-Sinencio
2020 J jnl
A Fully Integrated Maximum Power Tracking Combiner for Energy Harvesting IoT Applications.
IEEE Trans. Ind. Electron.
Johan J. Estrada-López, Amr Abuellil, Alfredo Costilla-Reyes, Mohamed Abouzied, Sungjun Yoon, Edgar Sánchez-Sinencio
2020 C conf
A Harmonic-Canceling Synthesizer using Skew-Circulant-Matrix-Based Coefficient Generator.
ISCAS
Guillermo G. Garayar-Leyva, Hatem Osman, Johan J. Estrada-López, Edgar Sánchez-Sinencio
2020 J jnl
A PVT-Resilient, Highly-Linear Fifth-Order Ring-Oscillator-Based Filter.
IEEE Trans. Circuits Syst.
Hatem Osman, Edgar Sánchez-Sinencio
2020 J jnl
A Reconfigurable Rectifier With Optimal Loading Point Determination for RF Energy Harvesting From -22 dBm to -2 dBm.
IEEE Trans. Circuits Syst. II Express Briefs
Zizhen Zeng, Johan J. Estrada-López, Mohamed Abouzied, Edgar Sánchez-Sinencio
2020 J jnl
A Stabilizing Centralized Controller for On-Chip Power Delivery Networks.
IEEE Trans. Circuits Syst. II Express Briefs
Joseph Riad, Peng Li, Edgar Sánchez-Sinencio
2020 J jnl
Breaking Analog Locking Techniques.
IEEE Trans. Very Large Scale Integr. Syst.
Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Amr Abuellil, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran
2020 C conf
Dynamic Heterogeneous Voltage Regulation for Systolic Array-Based DNN Accelerators.
ICCD
Jianhao Chen, Joseph Riad, Edgar Sánchez-Sinencio, Peng Li
2020 J jnl
Multiple-Input Harvesting Power Management Unit With Enhanced Boosting Scheme for IoT Applications.
IEEE Trans. Ind. Electron.
Amr Abuellil, Johan J. Estrada-López, Aditya Bommireddipalli, Alfredo Costilla-Reyes, Zizhen Zeng, Edgar Sánchez-Sinencio
2020 J jnl
Power-Scaling Output-Compensated Three-Stage OTAs for Wide Load Range Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Joseph Riad, Johan J. Estrada-López, Ivan R. Padilla-Cantoya, Edgar Sánchez-Sinencio
2020 A conf
Schmitt Trigger-Based Key Provisioning for Locking Analog/RF Integrated Circuits.
ITC
Adriana C. Sanabria-Borbon, Nithyashankari Gummidipoondi Jayasankaran, Sir Yee Lee, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan (JV) Rajendran
2020 — conf
Variation-Aware Heterogeneous Voltage Regulation for Multi-Core Systems-on-a-Chip with On-Chip Machine Learning.
ISQED
Joseph Riad, Jianhao Chen, Edgar Sánchez-Sinencio, Peng Li
2020 J jnl
Wien Oscillator Using Organic Enzyme-Chemiresistors for Fused Measurement of Glucose and Lactate.
Adv. Intell. Syst.
John R. Aggas, Edgar Sánchez-Sinencio, Anthony Guiseppi-Elie
2019 J jnl
A Unified Amplifier-Based CC-CV Linear Charger for Energy-Constrained Low-Power Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Kyoohyun Noh, Minglei Zhang, Edgar Sánchez-Sinencio
2019 J jnl
An On-Chip Built-in Linearity Estimation Methodology and Hardware Implementation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Congyin Shi, Edgar Sánchez-Sinencio
2019 A conf
Breaking Analog Locking Techniques via Satisfiability Modulo Theories.
ITC
Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Amr Abuellil, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran
2019 J jnl
Design of Sub-Gigahertz Reconfigurable RF Energy Harvester From -22 to 4 dBm With 99.8% Peak MPPT Power Efficiency.
IEEE J. Solid State Circuits
Zizhen Zeng, Shanpu Shen, Xiaopeng Zhong, Xing Li, Chi-Ying Tsui, Amine Bermak, Ross D. Murch, Edgar Sánchez-Sinencio
2019 J jnl
Highly Linear Low-Power Wireless RF Receiver for WSN.
IEEE Trans. Very Large Scale Integr. Syst.
Omar Elsayed, Jorge Zarate-Roldan, Amr Abuellil, Faisal Abdel-Latif Hussien, Ahmed Eladawy, Edgar Sánchez-Sinencio
2019 J jnl
Power Management for Multicore Processors via Heterogeneous Voltage Regulation and Machine Learning Enabled Adaptation.
IEEE Trans. Very Large Scale Integr. Syst.
Xin Zhan, Jianhao Chen, Edgar Sánchez-Sinencio, Peng Li
2019 J jnl
Reconfigurable System for Electromagnetic Energy Harvesting With Inherent Activity Sensing Capabilities for Wearable Technology.
IEEE Trans. Circuits Syst. II Express Briefs
Alfredo Costilla-Reyes, Amr Abuellil, Johan J. Estrada-López, Salvador Carreon-Bautista, Edgar Sánchez-Sinencio
2019 J jnl
Taming the Stability-Constrained Performance Optimization Challenge of Distributed On-Chip Voltage Regulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xin Zhan, Peng Li, Edgar Sánchez-Sinencio
2018 J jnl
A 13.56-MHz CMOS Active Rectifier With a Voltage Mode Switched-Offset Comparator for Implantable Medical Devices.
IEEE Trans. Very Large Scale Integr. Syst.
Kyoohyun Noh, Judy M. Amanor-Boadu, Minglei Zhang, Edgar Sánchez-Sinencio
2018 J jnl
A Built-In Self-Test and In Situ Analog Circuit Optimization Platform.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sanghoon Lee, Congyin Shi, Jiafan Wang, Adriana C. Sanabria-Borbon, Hatem Osman, Jiang Hu, Edgar Sánchez-Sinencio
2018 J jnl
A Switched Capacitor Energy Harvester Based on a Single-Cycle Criterion for MPPT to Eliminate Storage Capacitor.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xiaosen Liu, Krishnan Ravichandran, Edgar Sánchez-Sinencio
2018 J jnl
A Time-Domain Digital-Intensive Built-In Tester for Analog Circuits.
J. Electron. Test.
Congyin Shi, Sanghoon Lee, Sergio Soto Aguilar, Edgar Sánchez-Sinencio
2018 J jnl
An Area Efficient Thermal Energy Harvester With Reconfigurable Capacitor Charge Pump for IoT Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Sungjun Yoon, Salvador Carreon-Bautista, Edgar Sánchez-Sinencio
2018 J jnl
An Efficient and Fast Li-Ion Battery Charging System Using Energy Harvesting or Conventional Sources.
IEEE Trans. Ind. Electron.
Judy M. Amanor-Boadu, Mohamed Abouzied, Edgar Sánchez-Sinencio
2018 J jnl
An Integrated Concurrent Multiple-Input Self-Startup Energy Harvesting Capacitive-Based DC Adder Combiner.
IEEE Trans. Ind. Electron.
Mohamed Abouzied, Hatem Osman, Vaibhav A. Vaidya, Krishnan Ravichandran, Edgar Sánchez-Sinencio
2018 J jnl
Design Space Exploration of Distributed On-Chip Voltage Regulation Under Stability Constraint.
IEEE Trans. Very Large Scale Integr. Syst.
Xin Zhan, Joseph Riad, Peng Li, Edgar Sánchez-Sinencio
2018 J jnl
Search for Optimal Pulse Charging Parameters for Li-Ion Polymer Batteries Using Taguchi Orthogonal Arrays.
IEEE Trans. Ind. Electron.
Judy M. Amanor-Boadu, Anthony Guiseppi-Elie, Edgar Sánchez-Sinencio
2018 — conf
Surrogate-based Optimization-aided Design for Low Power Analog Circuits.
MWSCAS
Sergio Soto Aguilar, Adriana C. Sanabria-Borbon, Edgar Sánchez-Sinencio
2018 C conf
Technology Enabling Circuits and Systems for the Internet-of-Things: An Overview.
ISCAS
Johan J. Estrada-López, Amr Abuellil, Alfredo Costilla-Reyes, Edgar Sánchez-Sinencio
2018 J jnl
Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction.
IACR Cryptol. ePrint Arch.
Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran
2018 A conf
Towards provably-secure analog and mixed-signal locking against overproduction.
ICCAD
Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran
2017 — conf
21.4 A reduced-order sliding-mode controller with an auxiliary PLL frequency discriminator for ultrasonic electric scalpels.
ISSCC
Xiaosen Liu, Adrian I. Colli-Menchi, Edgar Sánchez-Sinencio
2017 J jnl
A 0.8-1.2 V 10-50 MS/s 13-bit Subranging Pipelined-SAR ADC Using a Temperature-Insensitive Time-Based Amplifier.
IEEE J. Solid State Circuits
Minglei Zhang, Kyoohyun Noh, Xiaohua Fan, Edgar Sánchez-Sinencio
2017 J jnl
A Fully Integrated Reconfigurable Self-Startup RF Energy-Harvesting System With Storage Capability.
IEEE J. Solid State Circuits
Mohamed Abouzied, Krishnan Ravichandran, Edgar Sánchez-Sinencio
2017 J jnl
An All-MOSFET Sub-1-V Voltage Reference With a - 51 -dB PSR up to 60 MHz.
IEEE Trans. Very Large Scale Integr. Syst.
Nashiru Alhassan, Zekun Zhou, Edgar Sánchez-Sinencio
2017 J jnl
An All-MOSFET Voltage Reference With -50-dB PSR at 80 MHz for Low-Power SoC Design.
IEEE Trans. Circuits Syst. II Express Briefs
Nashiru Alhassan, Zekun Zhou, Edgar Sánchez-Sinencio
2017 — conf
Analog filter design: Current design techniques and trends.
CICC
Edgar Sánchez-Sinencio
2017 — conf
Efficient use of gain-bandwidth product in active filters: Gm-C and Active-R alternatives.
LASCAS
Adriana C. Sanabria-Borbon, Edgar Sánchez-Sinencio
2017 J jnl
Guest Editorial Special Issue on Circuits and Systems for the Internet of Things - From Sensing to Sensemaking.
IEEE Trans. Circuits Syst. I Regul. Pap.
Massimo Alioto, Edgar Sánchez-Sinencio, Alberto L. Sangiovanni-Vincentelli
2017 A conf
Noise-sensitive feedback loop identification in linear time-varying analog circuits.
DATE
Ang Li, Peng Li, Tingwen Huang, Edgar Sánchez-Sinencio
2017 J jnl
On-Chip Two-Tone Synthesizer Based on a Mixing-FIR Architecture.
IEEE J. Solid State Circuits
Congyin Shi, Edgar Sánchez-Sinencio
2017 — conf
Session 22 overview: Harvesting and wireless power.
ISSCC
Stefano Stanzione, Edgar Sánchez-Sinencio, Axel Thomsen
2017 A conf
Thwarting analog IC piracy via combinational locking.
ITC
Jiafan Wang, Congyin Shi, Adriana C. Sanabria-Borbon, Edgar Sánchez-Sinencio, Jiang Hu
2017 J jnl
Ultrasonic Electric Scalpels Based on a Sliding-Mode Controller With an Auxiliary PLL Frequency Discriminator.
IEEE Trans. Biomed. Circuits Syst.
Xiaosen Liu, Adrian I. Colli-Menchi, Edgar Sánchez-Sinencio
2016 — conf
21.1 A single-cycle MPPT charge-pump energy harvester using a thyristor-based VCO without storage capacitor.
ISSCC
Xiaosen Liu, Edgar Sánchez-Sinencio
2016 J jnl
A Capacitor-Less LDO With High-Frequency PSR Suitable for a Wide Range of On-Chip Capacitive Loads.
IEEE Trans. Very Large Scale Integr. Syst.
Jorge Zarate-Roldan, Mengde Wang, Joselyn Torres, Edgar Sánchez-Sinencio
2016 J jnl
A Highly Efficient Reconfigurable Charge Pump Energy Harvester With Wide Harvesting Range and Two-Dimensional MPPT for Internet of Things.
IEEE J. Solid State Circuits
Xiaosen Liu, Lilly Huang, Krishnan Ravichandran, Edgar Sánchez-Sinencio
2016 J jnl
An Autonomous Energy Harvesting Power Management Unit With Digital Regulation for IoT Applications.
IEEE J. Solid State Circuits
Salvador Carreon-Bautista, Lilly Huang, Edgar Sánchez-Sinencio
2016 A* conf
Distributed on-chip regulation: theoretical stability foundation, over-design reduction and performance optimization.
DAC
Xin Zhan, Peng Li, Edgar Sánchez-Sinencio
2016 J jnl
Introduction to the December Special Issue on the 2016 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits
Edgar Sánchez-Sinencio, Jan Mulder, Antonio Liscidini, Eric A. M. Klumperink, Elad Alon
2015 J jnl
150-850 MHz High-Linearity Sine-wave Synthesizer Architecture Based on FIR Filter Approach and SFDR Optimization.
IEEE Trans. Circuits Syst. I Regul. Pap.
Congyin Shi, Edgar Sánchez-Sinencio
2015 — conf
20.7 A 0.45-to-3V reconfigurable charge-pump energy harvester with two-dimensional MPPT for Internet of Things.
ISSCC
Xiaosen Liu, Edgar Sánchez-Sinencio
2015 J jnl
A Highly Efficient Ultralow Photovoltaic Power Harvesting System With MPPT for Internet of Things Smart Nodes.
IEEE Trans. Very Large Scale Integr. Syst.
Xiaosen Liu, Edgar Sánchez-Sinencio
2015 J jnl
A Home Sleep Apnea Screening Device With Time-Domain Signal Processing and Autonomous Scoring Capability.
IEEE Trans. Biomed. Circuits Syst.
Jiayi Jin, Edgar Sánchez-Sinencio
2015 J jnl
A Power Management Unit With 40 dB Switching-Noise-Suppression for a Thermal Harvesting Array.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jorge Zarate-Roldan, Salvador Carreon-Bautista, Alfredo Costilla-Reyes, Edgar Sánchez-Sinencio
2015 J jnl
An 86% Efficiency 12 µW Self-Sustaining PV Energy Harvesting System With Hysteresis Regulation and Time-Domain MPPT for IOT Smart Nodes.
IEEE J. Solid State Circuits
Xiaosen Liu, Edgar Sánchez-Sinencio
2015 J jnl
An Automatic Resonance Tracking Scheme With Maximum Power Transfer for Piezoelectric Transducers.
IEEE Trans. Ind. Electron.
Xiaosen Liu, Adrian Colli-Menchi, James G. R. Gilbert, Daniel A. Friedrichs, Keith Malang, Edgar Sánchez-Sinencio
2015 — conf
Built-In Self Optimization for Variation Resilience of Analog Filters.
ISVLSI
Jiafan Wang, Congyin Shi, Edgar Sánchez-Sinencio, Jiang Hu
2015 J jnl
Low power complementary metal-oxide semiconductor class-G audio amplifier with gradual power supply switching.
IET Circuits Devices Syst.
Bharadvaj Bhamidipati, Adrian Colli-Menchi, Edgar Sánchez-Sinencio
2014 J jnl
A Feed-Forward Power-Supply Noise Cancellation Technique for Single-Ended Class-D Audio Amplifiers.
IEEE J. Solid State Circuits
Adrian Colli-Menchi, Joselyn Torres, Edgar Sánchez-Sinencio
2014 — conf
A switched mode Li-ion battery charger with multiple energy harvesting systems simultaneously used as input sources.
MWSCAS
Judy M. Amanor-Boadu, Mohamed A. Abouzied, Salvador Carreon-Bautista, Roland Ribeiro, Xiaosen Liu, Edgar Sánchez-Sinencio
2014 J jnl
An Energy-Efficient Time-Domain Asynchronous 2 b/Step SAR ADC With a Hybrid R-2R/C-3C DAC Structure.
IEEE J. Solid State Circuits
Jiayi Jin, Yang Gao, Edgar Sánchez-Sinencio
2014 — conf
An ultra-low power power management unit with -40dB switching-noise-suppression for a 3×3 thermoelectric generator array with 57% maximum end-to-end efficiency.
CICC
Jorge Zarate-Roldan, Salvador Carreon-Bautista, Alfredo Costilla-Reyes, Edgar Sánchez-Sinencio
2014 J jnl
Boost Converter With Dynamic Input Impedance Matching for Energy Harvesting With Multi-Array Thermoelectric Generators.
IEEE Trans. Ind. Electron.
Salvador Carreon-Bautista, Ahmed Eladawy, Ahmed Nader Mohieldin, Edgar Sánchez-Sinencio
2014 J jnl
Electromagnetic Interference Resisting Operational Amplifier.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jingjing Yu, Ahmed Amer, Edgar Sánchez-Sinencio
2014 — conf
Reduced clock harmonic distortion technique in maximum tunable switched-R-MOSFET-C filters.
MWSCAS
Arunvenkatesh Alagappan, Sergio Soto Aguilar, Edgar Sánchez-Sinencio
2014 — conf
Smart nodes of internet of things (IoT): a hardware perspective view & implementation.
ACM Great Lakes Symposium on VLSI
Edgar Sánchez-Sinencio
2014 — conf
SmartShelter: A Sustainable power system design using energy harvesting techniques.
MWSCAS
Leticia Ibarra, Benjamin Hilton, Mehna Nawal, Salvador Carreon-Bautista, Mohamed Abouzied, Xiaosen Liu, Roland Ribeiro, Judy Amanor-Badu, Ethan Miller, Jorge Vanegas, Edgar Sánchez-Sinencio
2014 J jnl
Survey of integrated-circuit-oscillator phase-noise analysis.
Int. J. Circuit Theory Appl.
Erik Pankratz, Edgar Sánchez-Sinencio
2014 — conf
Welcome to MWSCAS 2014.
MWSCAS
José Silva-Martínez, Edgar Sánchez-Sinencio, José G. Delgado-Frias, Randall L. Geiger
2013 J jnl
A Low-Power Configurable Neural Recording System for Epileptic Seizure Detection.
IEEE Trans. Biomed. Circuits Syst.
Chengliang Qian, Jess Shi, Jordi Parramon, Edgar Sánchez-Sinencio
2013 J jnl
A Spur-Frequency-Boosting PLL With a -74 dBc Reference-Spur Suppression in 90 nm Digital CMOS.
IEEE J. Solid State Circuits
Mohamed M. Elsayed, Mohammed M. Abdul-Latif, Edgar Sánchez-Sinencio
2013 — conf
A biopotential amplifier with improved common mode gain.
LASCAS
Reza Abdullah, Edgar Sánchez-Sinencio
2013 J jnl
Current-Reused 2.4-GHz Direct-Modulation Transmitter With On-Chip Automatic Tuning.
IEEE Trans. Very Large Scale Integr. Syst.
Hesam Amir Aslanzadeh, Erik John Pankratz, Chinmaya Mishra, Edgar Sánchez-Sinencio
2012 J jnl
A 2-GHz Highly Linear Efficient Dual-Mode BiCMOS Power Amplifier Using a Reconfigurable Matching Network.
IEEE J. Solid State Circuits
Hajir Hedayati, Mohamed Mobarak, Guillaume Varin, Philippe Meunier, Patrice Gamand, Edgar Sánchez-Sinencio, Kamran Entesari
2012 J jnl
Advanced Quenching Techniques for Super-Regenerative Radio Receivers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Félix O. Fernandez-Rodriguez, Edgar Sánchez-Sinencio
2012 — conf
Challenges of printed electronics on flexible substrates.
MWSCAS
Joseph S. Chang, Tong Ge, Edgar Sánchez-Sinencio
2012 J jnl
Low Phase Noise Wide Tuning Range N-Push Cyclic-Coupled Ring Oscillators.
IEEE J. Solid State Circuits
Mohammed M. Abdul-Latif, Edgar Sánchez-Sinencio
2012 J jnl
Multiloop High-Power-Supply-Rejection Quadrature Ring Oscillator.
IEEE J. Solid State Circuits
Erik Pankratz, Edgar Sánchez-Sinencio
2012 — conf
Ultra-low-voltage power management unit for thermal energy harvesting applications.
NEWCAS
Moataz Abdelfattah, Ahmed Nader Mohieldin, Ahmed Emira, Ahmed K. Hussien, Edgar Sánchez-Sinencio
2011 — conf
A 0.6-to-200MSPS speed reconfigurable and 1.9-to-27mW power scalable 10bit ADC.
ESSCIRC
Heng Zhang, Junhua Tan, Chao Zhang, Hongbo Chen, Edgar Sánchez-Sinencio
2011 J jnl
A 0.8 ps DNL Time-to-Digital Converter With 250 MHz Event Rate in 65 nm CMOS for Time-Mode-Based Sigma Delta Modulator.
IEEE J. Solid State Circuits
Mohamed M. Elsayed, Vijay Dhanasekaran, Manisha Gambhir, José Silva-Martínez, Edgar Sánchez-Sinencio
2011 J jnl
A Continuous Time Multi-Bit Delta Sigma ADC Using Time Domain Quantizer and Feedback Element.
IEEE J. Solid State Circuits
Vijay Dhanasekaran, Manisha Gambhir, Mohamed M. Elsayed, Edgar Sánchez-Sinencio, José Silva-Martínez, Chinmaya Mishra, Lei Chen, Erik Pankratz
2011 J jnl
A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Didem Zeliha Turker, Sunil P. Khatri, Edgar Sánchez-Sinencio
2011 J jnl
A Low-Power High-PSRR Clock-Free Current-Controlled Class-D Audio Amplifier.
IEEE J. Solid State Circuits
Joselyn Torres, Adrian Colli-Menchi, Miguel Angel Rojas González, Edgar Sánchez-Sinencio
2011 J jnl
A Micropower Low-Noise Neural Recording Front-End Circuit for Epileptic Seizure Detection.
IEEE J. Solid State Circuits
Chengliang Qian, Jordi Parramon, Edgar Sánchez-Sinencio
2011 J jnl
A Wideband Millimeter-Wave Frequency Synthesis Architecture Using Multi-Order Harmonic-Synthesis and Variable N -Push Frequency Multiplication.
IEEE J. Solid State Circuits
Mohammed M. Abdul-Latif, Mohamed M. Elsayed, Edgar Sánchez-Sinencio
2011 — conf
A fully integrated highly linear efficient power amplifier in 0.25µm BiCMOS technology for wireless applications.
CICC
Hajir Hedayati, Mohamed Mobarak, Guillaume Varin, Philippe Meunier, Patrice Gamand, Edgar Sánchez-Sinencio, Kamran Entesari
2011 J jnl
An Inductor-Less Noise-Cancelling Broadband Low Noise Amplifier With Composite Transistor Pair in 90 nm CMOS Technology.
IEEE J. Solid State Circuits
Mohamed El-Nozahi, Ahmed A. Helmy, Edgar Sánchez-Sinencio, Kamran Entesari
2011 J jnl
Linearization Techniques for CMOS Low Noise Amplifiers: A Tutorial.
IEEE Trans. Circuits Syst. I Regul. Pap.
Heng Zhang, Edgar Sánchez-Sinencio
2010 — conf
A 140mA 90nm CMOS low drop-out regulator with -56dB power supply rejection at 10MHz.
CICC
Ahmed Amer, Edgar Sánchez-Sinencio
2010 — conf
A 470μW clock-free current-controlled class D amplifier with 0.02% THD+N and 82dB PSRR.
ESSCIRC
Joselyn Torres, Adrian Colli-Menchi, Miguel Angel Rojas González, Edgar Sánchez-Sinencio
2010 J jnl
A Low THD, Low Power, High Output-Swing Time-Mode-Based Tunable Oscillator Via Digital Harmonic-Cancellation Technique.
IEEE J. Solid State Circuits
Mohamed M. Elsayed, Edgar Sánchez-Sinencio
2010 J jnl
A Millimeter-Wave (23-32 GHz) Wideband BiCMOS Low-Noise Amplifier.
IEEE J. Solid State Circuits
Mohamed El-Nozahi, Edgar Sánchez-Sinencio, Kamran Entesari
2010 J jnl
Attenuation-Predistortion Linearization of CMOS OTAs With Digital Correction of Process Variations in OTA-C Filter Applications.
IEEE J. Solid State Circuits
Mohamed Mobarak, Marvin Onabajo, José Silva-Martínez, Edgar Sánchez-Sinencio
2010 J jnl
High PSR Low Drop-Out Regulator With Feed-Forward Ripple Cancellation Technique.
IEEE J. Solid State Circuits
Mohamed El-Nozahi, Ahmed Amer, Joselyn Torres, Kamran Entesari, Edgar Sánchez-Sinencio
2009 J jnl
A 1-V +31 dBm IIP3, Reconfigurable, Continuously Tunable, Power-Adjustable Active-RC LPF.
IEEE J. Solid State Circuits
Hesam Amir Aslanzadeh, Erik John Pankratz, Edgar Sánchez-Sinencio
2009 — conf
A 20MHz BW 68dB DR CT ΔΣ ADC based on a multi-bit time-domain quantizer and feedback element.
ISSCC
Vijay Dhanasekaran, Manisha Gambhir, Mohamed M. Elsayed, Edgar Sánchez-Sinencio, José Silva-Martínez, Chinmaya Mishra, Lei Chen, Erik Pankratz
2009 — conf
A 25mA 0.13µm CMOS LDO regulator with power-supply rejection better than -56dB up to 10MHz using a feedforward ripple-cancellation technique.
ISSCC
Mohamed El-Nozahi, Ahmed Amer, Joselyn Torres, Kamran Entesari, Edgar Sánchez-Sinencio
2009 J jnl
A Low-Power, Linearized, Ultra-Wideband LNA Design Technique.
IEEE J. Solid State Circuits
Heng Zhang, Xiaohua Fan, Edgar Sánchez-Sinencio
2009 J jnl
An On-Chip Loopback Block for RF Transceiver Built-In Test.
IEEE Trans. Circuits Syst. II Express Briefs
Marvin Onabajo, José Silva-Martínez, Félix O. Fernandez-Rodriguez, Edgar Sánchez-Sinencio
2009 J jnl
Design of Three-Stage Class-AB 16ΩHeadphone Driver Capable of Handling Wide Range of Load Capacitance.
IEEE J. Solid State Circuits
Vijay Dhanasekaran, José Silva-Martínez, Edgar Sánchez-Sinencio
2009 J jnl
Low-Power High-Efficiency Class D Audio Power Amplifiers.
IEEE J. Solid State Circuits
Miguel Angel Rojas González, Edgar Sánchez-Sinencio
2009 — conf
New applications and technology scaling driving next generation A/D converters.
ECCTD
Heng Zhang, Mohamed Mostafa Elsayed, Edgar Sánchez-Sinencio
2009 J jnl
Power-Aware Multiband-Multistandard CMOS Receiver System-Level Budgeting.
IEEE Trans. Circuits Syst. II Express Briefs
Mohamed El-Nozahi, Edgar Sánchez-Sinencio, Kamran Entesari
2009 J jnl
RF Oscillator Based on a Passive RC Bandpass Filter.
IEEE J. Solid State Circuits
Sang Wook Park, Edgar Sánchez-Sinencio
2009 J jnl
System and Circuit Design for an MB-OFDM UWB Frequency Synthesizer.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chinmaya Mishra, Alberto Valdes-Garcia, Edgar Sánchez-Sinencio, José Silva-Martínez
2009 — conf
Two Class-D audio amplifiers with 89/90% efficiency and 0.02/0.03% THD+N consuming less than 1mW of quiescent power.
ISSCC
Miguel Angel Rojas González, Edgar Sánchez-Sinencio
2008 — conf
A 1.2mW 1.6Vpp-Swing Class-AB 16Ω Headphone Driver Capable of Handling Load Capacitance up to 22nF.
ISSCC
Vijay Dhanasekaran, José Silva-Martínez, Edgar Sánchez-Sinencio
2008 J jnl
A Broadband CMOS Amplitude Detector for On-Chip RF Measurements.
IEEE Trans. Instrum. Meas.
Alberto Valdes-Garcia, Radhika Venkatasubramanian, José Silva-Martínez, Edgar Sánchez-Sinencio
2008 J jnl
A Current Injection Built-In Test Technique for RF Low-Noise Amplifiers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xiaohua Fan, Marvin Onabajo, Félix O. Fernandez-Rodriguez, José Silva-Martínez, Edgar Sánchez-Sinencio
2008 J jnl
A Noise Reduction and Linearity Improvement Technique for a Differential Cascode LNA.
IEEE J. Solid State Circuits
Xiaohua Fan, Heng Zhang, Edgar Sánchez-Sinencio
2008 J jnl
A Robust and Scalable Constant- g
IEEE Trans. Circuits Syst. I Regul. Pap.
Tongyu Song, Jingyu Hu, Xiaohong Li, Edgar Sánchez-Sinencio, Shouli Yan
2008 — conf
A low power 1.3GHz dual-path current mode Gm-C filter.
CICC
Manisha Gambhir, Vijay Dhanasekaran, José Silva-Martínez, Edgar Sánchez-Sinencio
2008 J jnl
Applications of Multipath Transform-Domain Charge-Sampling Wide-Band Receivers.
IEEE Trans. Circuits Syst. II Express Briefs
Pradeep Kotte Prakasam, Mandar Kulkarni, Xi Chen, Zhuizhuan Yu, Sebastian Hoyos, José Silva-Martínez, Edgar Sánchez-Sinencio
2007 J jnl
A 1.1 GHz Fifth Order Active-LC Butterworth Type Equalizing Filter.
IEEE J. Solid State Circuits
Vijay Dhanasekaran, Manisha Gambhir, José Silva-Martínez, Edgar Sánchez-Sinencio
2007 C conf
A Low-Power Frequency Synthesizer with Quadrature Signal Generation for 2.4 GHz Zigbee Transceiver Applications.
ISCAS
Rangakrishnan Srinivasan, Didem Zeliha Turker, Sang Wook Park, Edgar Sánchez-Sinencio
2007 J jnl
A general framework for evaluating nonlinearity, noise and dynamic range in continuous-time OTA-C filters for computer-aided design and optimization.
Int. J. Circuit Theory Appl.
Slawomir Koziel, A. Ramachandran, Stanislaw Szczepanski, Edgar Sánchez-Sinencio
2007 J jnl
An 11-Band 3-10 GHz Receiver in SiGe BiCMOS for Multiband OFDM UWB Communication.
IEEE J. Solid State Circuits
Alberto Valdes-Garcia, Chinmaya Mishra, Faramarz Bahmani, José Silva-Martínez, Edgar Sánchez-Sinencio
2007 J jnl
An Accurate Automatic Quality-Factor Tuning Scheme for Second-Order
IEEE Trans. Circuits Syst. I Regul. Pap.
Faramarz Bahmani, Teresa Serrano-Gotarredona, Edgar Sánchez-Sinencio
2007 J jnl
Design of a Class D Audio Amplifier IC Using Sliding Mode Control and Negative Feedback.
IEEE Trans. Consumer Electron.
Miguel Angel Rojas González, Edgar Sánchez-Sinencio
2007 J jnl
Full On-Chip CMOS Low-Dropout Voltage Regulator.
IEEE Trans. Circuits Syst. I Regul. Pap.
Robert Jon Milliken, José Silva-Martínez, Edgar Sánchez-Sinencio
2007 J jnl
Low THD bandpass-based oscillator using multilevel hard limiter.
IET Circuits Devices Syst.
Faramarz Bahmani, Edgar Sánchez-Sinencio
2007 J jnl
Low-Power Architecture and Circuit Techniques for High-Boost Wide-Band G
IEEE Trans. Circuits Syst. I Regul. Pap.
Manisha Gambhir, Vijay Dhanasekaran, José Silva-Martínez, Edgar Sánchez-Sinencio
2007 J jnl
Nonlinear Shaping SC Oscillator With Enhanced Linearity.
IEEE J. Solid State Circuits
Sang Wook Park, José L. Ausín, Faramarz Bahmani, Edgar Sánchez-Sinencio
2007 C conf
THD+Noise Estimation in Class-D Amplifiers.
ISCAS
Burak Kelleci, Edgar Sánchez-Sinencio, Aydin I. Karsilayan
2006 J jnl
A 10-bit 44-MS/s 20-mW configurable time-interleaved pipeline ADC for a dual-mode 802.11b/Bluetooth receiver.
IEEE J. Solid State Circuits
Bo Xia, Alberto Valdes-Garcia, Edgar Sánchez-Sinencio
2006 J jnl
A Stable Loss Control Feedback Loop for VCO Amplitude Tuning.
IEEE Trans. Circuits Syst. I Regul. Pap.
Faramarz Bahmani, Edgar Sánchez-Sinencio
2006 J jnl
An Integrated Frequency Response Characterization System With a Digital Interface for Analog Testing.
IEEE J. Solid State Circuits
Alberto Valdes-Garcia, Faisal Abdel-Latif Hussien, José Silva-Martínez, Edgar Sánchez-Sinencio
2006 J jnl
CMOS RF receiver system design: a systematic approach.
IEEE Trans. Circuits Syst. I Regul. Pap.
Wenjun Sheng, Ahmed Emira, Edgar Sánchez-Sinencio
2006 J jnl
Chameleon: a dual-mode 802.11b/Bluetooth receiver system design.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ahmed A. Emira, Alberto Valdes-Garcia, Bo Xia, A. N. Mohieldin, Ari Yakov Valero-López, Sung Tae Moon, Chunyu Xin, Edgar Sánchez-Sinencio
2006 J jnl
Frequency-dependent harmonic-distortion analysis of a linearized cross-coupled CMOS OTA and its application to OTA-C filters.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jianlong Chen, Edgar Sánchez-Sinencio, José Silva-Martínez
2006 J jnl
On-Chip Testing Techniques for RF Wireless Transceivers.
IEEE Des. Test Comput.
Alberto Valdes-Garcia, José Silva-Martínez, Edgar Sánchez-Sinencio
2006 J jnl
Robust highly linear high-frequency CMOS OTA with IM3 below - 70 dB at 26 MHz.
IEEE Trans. Circuits Syst. I Regul. Pap.
Wenchang Huang, Edgar Sánchez-Sinencio
2006 C conf
Second order dynamic element matching technique for low oversampling delta sigma ADC.
ISCAS
A. K. Gupta, Edgar Sánchez-Sinencio, S. Karthikeyan, Wern Ming Koe, Yong-In Park
2006 J jnl
Self-calibrated quadrature generator for WLAN multistandard frequency synthesizer.
IEEE J. Solid State Circuits
Ari Yakov Valero-López, Sung Tae Moon, Edgar Sánchez-Sinencio
2005 Misc conf
A CMOS RF RMS Detector for Built-in Testing of Wireless Transceivers.
VTS
Alberto Valdes-Garcia, Radhika Venkatasubramanian, Rangakrishnan Srinivasan, José Silva-Martínez, Edgar Sánchez-Sinencio
2005 J jnl
A capacitor cross-coupled common-gate low-noise amplifier.
IEEE Trans. Circuits Syst. II Express Briefs
Wei Zhuo, Xiaoyong Li, Sudip Shekhar, Sherif H. K. Embabi, José Pineda de Gyvez, David J. Allstot, Edgar Sánchez-Sinencio
2005 — conf
A constant-g
ISCAS (3)
Shouli Yan, Jingyu Hu, Tongyu Song, Edgar Sánchez-Sinencio
2005 J jnl
A rail-to-rail amplifier input stage with ±0.35%g
IEEE Trans. Circuits Syst. I Regul. Pap.
Timothy Wayne Fischer, Aydin I. Karsilayan, Edgar Sánchez-Sinencio
2005 J jnl
An On-Chip Spectrum Analyzer for Analog Built-In Testing.
J. Electron. Test.
Marcia G. Méndez-Rivera, Alberto Valdes-Garcia, José Silva-Martínez, Edgar Sánchez-Sinencio
2005 — conf
Constant-g
ISCAS (3)
Shouli Yan, Jingyu Hu, Tongyu Song, Edgar Sánchez-Sinencio
2005 — conf
Feedforward reversed nested Miller compensation techniques for three-stage amplifiers.
ISCAS (3)
Feng Zhu, Shouli Yan, Jingyu Hu, Edgar Sánchez-Sinencio
2005 J jnl
Single Miller capacitor frequency compensation technique for low-power multistage amplifiers.
IEEE J. Solid State Circuits
Xiaohua Fan, Chinmaya Mishra, Edgar Sánchez-Sinencio
2004 — conf
3-22GHz CMOS distributed single-balanced mixer.
SoCC
Xiaohua Fan, Edgar Sánchez-Sinencio
2004 — conf
A configurable time-interleaved pipeline ADC for multi-standard wireless receivers.
ESSCIRC
Bo Xia, Alberto Valdes-Garcia, Edgar Sánchez-Sinencio
2004 J jnl
A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth.
IEEE J. Solid State Circuits
Shouli Yan, Edgar Sánchez-Sinencio
2004 — conf
A dual-mode low-pass filter for 802.11b/Bluetooth receiver.
ESSCIRC
Ahmed Nader Mohieldin, Edgar Sánchez-Sinencio
2004 J jnl
A fully parallel CMOS analog median filter.
IEEE Trans. Circuits Syst. II Express Briefs
Alejandro Díaz-Sánchez, Jaime Ramírez-Angulo, Antonio J. López-Martín, Edgar Sánchez-Sinencio
2004 — conf
A highly linear pseudo-differential transconductance [CMOS OTA].
ESSCIRC
Faramarz Bahmani, Edgar Sánchez-Sinencio
2004 — conf
A linearization technique for RF low noise amplifier.
ISCAS (4)
Chunyu Xin, Edgar Sánchez-Sinencio
2004 J jnl
A practical self-calibration scheme implementation for pipeline ADC.
IEEE Trans. Instrum. Meas.
Benoit Provost, Edgar Sánchez-Sinencio
2004 Misc conf
An On-Chip Transfer Function Characterization System for Analog Built-in Testing.
VTS
Alberto Valdes-Garcia, José Silva-Martínez, Edgar Sánchez-Sinencio
2004 J jnl
An RC time constant auto-tuning structure for high linearity continuous-time ΣΔ modulators and active filters.
IEEE Trans. Circuits Syst. I Regul. Pap.
Bo Xia, Shouli Yan, Edgar Sánchez-Sinencio
2004 — conf
Dynamic range, noise and linearity optimization of continuous-time OTA-C filters.
ICECS
Slawomir Koziel, A. Ramachandran, Stanislaw Szczepanski, Edgar Sánchez-Sinencio
2004 — conf
Frequency synthesizer for on-chip testing and automated tuning.
ISCAS (4)
Ari Yakov Valero-López, Alberto Valdes-Garcia, Edgar Sánchez-Sinencio
2004 — conf
Linearized CMOS OTA using active-error feedforward technique.
ISCAS (1)
Stanislaw Szczepanski, Slawomir Koziel, Edgar Sánchez-Sinencio
2004 — conf
Single Miller capacitor compensated multistage amplifiers for large capacitive load applications.
ISCAS (1)
Xiaohua Fan, Chinmaya Mishra, Edgar Sánchez-Sinencio
2003 J jnl
A 1.3-V 5-mW fully integrated tunable bandpass filter at 2.1 GHz in 0.35-μm CMOS.
IEEE J. Solid State Circuits
Fikret Dulger, Edgar Sánchez-Sinencio, José Silva-Martínez
2003 J jnl
A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier.
IEEE J. Solid State Circuits
Keliu Shu, Edgar Sánchez-Sinencio, José Silva-Martínez, Sherif H. K. Embabi
2003 J jnl
A 2.7-V 1.8-GHz fourth-order tunable LC bandpass filter based on emulation of magnetically coupled resonators.
IEEE J. Solid State Circuits
Ahmed N. Mohieldin, Edgar Sánchez-Sinencio, José Silva-Martínez
2003 J jnl
A 3-V, 0.35-μm CMOS Bluetooth receiver IC.
IEEE J. Solid State Circuits
Wenjun Sheng, Bo Xia, Ahmed E. Emira, Chunyu Xin, Ari Yakov Valero-López, Sung Tae Moon, Edgar Sánchez-Sinencio
2003 J jnl
A GFSK demodulator for low-IF Bluetooth receiver.
IEEE J. Solid State Circuits
Bo Xia, Chunyu Xin, Wenjun Sheng, Ari Yakov Valero-López, Edgar Sánchez-Sinencio
2003 J jnl
A fully balanced pseudo-differential OTA with common-mode feedforward and inherent common-mode feedback detector.
IEEE J. Solid State Circuits
Ahmed Nader Mohieldin, Edgar Sánchez-Sinencio, José Silva-Martínez
2003 — conf
A low-power CMOS complex filter for Bluetooth with frequency tuning.
ISCAS (1)
Ahmed Emira, Edgar Sánchez-Sinencio
2003 J jnl
A pseudo differential complex filter for Bluetooth with frequency tuning.
IEEE Trans. Circuits Syst. II Express Briefs
Ahmed A. Emira, Edgar Sánchez-Sinencio
2003 J jnl
A wide input bandwidth 7-bit 300-MSample/s folding and current-mode interpolating ADC.
IEEE J. Solid State Circuits
Yunchu Li, Edgar Sánchez-Sinencio
2003 — conf
An Analog Integrated Circuit Design Laboratory.
MSE
Antonio F. Mondragón-Torres, Terry Mayhugh Jr., José Pineda de Gyvez, José Silva-Martínez, Edgar Sánchez-Sinencio
2003 J jnl
An enhanced adaptive Q-tuning scheme for a 100-MHz fully symmetric OTA-based bandpass filter.
IEEE J. Solid State Circuits
Praveen Kallam, Edgar Sánchez-Sinencio, Aydin Ilker Karsilayan
2003 J jnl
Nonlinear effects in pseudo differential OTAs with CMFB.
IEEE Trans. Circuits Syst. II Express Briefs
A. N. Mohieldin, Edgar Sánchez-Sinencio, José Silva-Martínez
2003 J jnl
On-chip ramp generators for mixed-signal BIST and ADC self-test.
IEEE J. Solid State Circuits
Benoit Provost, Edgar Sánchez-Sinencio
2003 J jnl
Switched-capacitor circuits with periodical nonuniform individual sampling.
IEEE Trans. Circuits Syst. II Express Briefs
José L. Ausín, J. Francisco Duque-Carrillo, Guido Torelli, Edgar Sánchez-Sinencio
2003 — conf
Variable gain amplifier with offset cancellation.
ACM Great Lakes Symposium on VLSI
Ahmed Emira, Edgar Sánchez-Sinencio
2002 J jnl
A 100-MHz 8-mW ROM-less quadrature direct digital frequency synthesizer.
IEEE J. Solid State Circuits
Ahmed Nader Mohieldin, Ahmed A. Emira, Edgar Sánchez-Sinencio
2002 — conf
A 2-V 11-bit incremental A/D converter using floating gate technique.
ISCAS (4)
A. N. Mohieldin, Ahmed Emira, Edgar Sánchez-Sinencio
2002 — conf
A 2.1-GHz monolithic frequency synthesizer with robust phase switching prescaler and loop capacitance scaling.
ISCAS (4)
Keliu Shu, Edgar Sánchez-Sinencio, José Silva-Martínez
2002 — conf
A 2.1GHz 1.3V 5mW programmable Q-enhancement LC bandpass biquad in 0.35μm CMOS.
CICC
Fikret Duelgel, Edgar Sánchez-Sinencio, Jose Silva-Martinez
2002 — conf
A 5-GHz prescaler using improved phase switching.
ISCAS (3)
Keliu Shu, Edgar Sánchez-Sinencio
2002 J jnl
A CMOS transconductance amplifier architecture with wide tuning range for very low frequency applications.
IEEE J. Solid State Circuits
Anand Veeravalli, Edgar Sánchez-Sinencio, José Silva-Martínez
2002 — conf
A mixed-mode IF GFSK demodulator for Bluetooth.
ISCAS (3)
Chunyu Xin, Bo Xia, Wenjun Sheng, Ari Yakov Valero-López, Edgar Sánchez-Sinencio
2002 — conf
A monolithic CMOS low-IF Bluetooth receiver.
CICC
Wenjun Sheng, Bo Xia, Ahmed Emira, Chunyu Xin, Sung Tae Moon, Ari Yakov Valero-López, Edgar Sánchez-Sinencio
2002 — conf
An auto-tuning structure for continuous time sigma-delta AD converter and high precision filters.
ISCAS (5)
Bo Xia, Shouli Yan, Edgar Sánchez-Sinencio
2002 — conf
An improved Q-tuning scheme and a fully symmetric OTA.
ISCAS (5)
Praveen Kallam, Edgar Sánchez-Sinencio, Aydin I. Karsilayan
2002 — conf
Design trade-offs of a symmetric linearized CMOS LC VCO.
ISCAS (4)
Fikret Dülger, Edgar Sánchez-Sinencio
2002 — conf
Design tradeoffs of CMOS current mirrors using one-equation for all-region model.
ISCAS (5)
Ahmed Emira, Edgar Sánchez-Sinencio, M. Schneider
2002 — conf
High-selectivity SC filters with continuous digital Q-factor programmability.
ISCAS (4)
José L. Ausín, Raquel Pérez-Aloe, J. Francisco Duque-Carrillo, Guido Torelli, Edgar Sánchez-Sinencio
2002 — conf
On-chip spectrum analyzer for built-in testing analog ICs.
ISCAS (5)
Marcia G. Méndez-Rivera, José Silva-Martínez, Edgar Sánchez-Sinencio
2002 J jnl
Transconductance amplifier structures with very small transconductances: a comparative design approach.
IEEE J. Solid State Circuits
Anand Veeravalli, Edgar Sánchez-Sinencio, José Silva-Martínez
2001 — conf
1.5 V 5.0 MHz switched capacitor circuits in 1.2 μm CMOS without voltage bootstrapper.
CICC
Lei Wang, Sherif H. K. Embabi, Edgar Sánchez-Sinencio
2001 — conf
A comparative study of digital ΣΔ modulators for fractional-N synthesis.
ICECS
Keliu Shu, Edgar Sánchez-Sinencio, Franco Maloberti, Udaykiran Eduri
2001 — conf
A low voltage operational transconductance amplifier using common mode feedforward for high frequency switched capacitor circuits.
ISCAS (1)
Asit Shankar, José Silva-Martínez, Edgar Sánchez-Sinencio
2001 — conf
Linear cellular neural networks.
ISCAS (3)
Federico Lobato-Lopez, José Silva-Martínez, Edgar Sánchez-Sinencio
2000 C conf
A fully parallel CMOS analog median filter.
ISCAS
Alejandro Díaz-Sánchez, Jaime Ramírez-Angulo, Antonio Lopez, Edgar Sánchez-Sinencio
2000 C conf
A programmable rail-to-rail constant-g
ISCAS
Shouli Yan, Edgar Sánchez-Sinencio
2000 C conf
Different operational transconductance amplifier topologies for obtaining very small transconductances.
ISCAS
Anand Veeravalli, Edgar Sánchez-Sinencio, José Silva-Martínez
2000 C conf
Periodical nonuniform individually sampled switched-capacitor circuits.
ISCAS
José L. Ausín, Juan F. Duque-Carillo, Guido Torelli, Edgar Sánchez-Sinencio, Franco Maloberti
1999 — conf
A low voltage fully differential nested Gm capacitance compensation amplifier: analysis and design.
ISCAS (2)
G. Xu, Sherif H. K. Embabi, P. Hao, Edgar Sánchez-Sinencio
1999 A conf
Auto-calibrating analog timer for on-chip testing.
ITC
Benoit Provost, Edgar Sánchez-Sinencio
1999 — conf
CMOS cryptosystem using a Lorenz chaotic oscillator.
ISCAS (5)
Octavio A. González, Gunhee Han, José Pineda de Gyvez, Edgar Sánchez-Sinencio
1998 — conf
A 1.8 V pseudo-differential switched-capacitor amplifier.
CICC
Zeki Sezgin Günay, Eric G. Soenen, Sherif H. K. Embabi, Edgar Sánchez-Sinencio
1998 — conf
A Unified Approach for a Time-Domain Built-In Self-Test Technique and Fault Detection.
Great Lakes Symposium on VLSI
Benoit Provost, Edgar Sánchez-Sinencio, Anna Maria Brosa
1998 — conf
A current-mode based field programmable analog array architecture for signal processing applications.
CICC
X. Quan, Sherif H. K. Embabi, Edgar Sánchez-Sinencio
1998 — conf
A parallel analog median filter.
ICECS
Alejandro Díaz-Sánchez, Jaime Ramírez-Angulo, Antonio Lopez, Edgar Sánchez-Sinencio
1998 J jnl
An accurate quality factor tuning scheme for IF and high-Q continuous-time filters.
IEEE J. Solid State Circuits
Jan-Michael Stevenson, Edgar Sánchez-Sinencio
1998 — conf
Efficient clock recovery architecture.
ICECS
Marcia G. Méndez-Rivera, Ari Yakov Valero-López, José Silva-Martínez, Edgar Sánchez-Sinencio
1998 J jnl
Low-voltage class AB buffers with quiescent current control.
IEEE J. Solid State Circuits
Fan You, Sherif H. K. Embabi, Edgar Sánchez-Sinencio
1998 J jnl
Time multiplexed color image processing based on a CNN with cell-state outputs.
IEEE Trans. Very Large Scale Integr. Syst.
Lei Wang, José Pineda de Gyvez, Edgar Sánchez-Sinencio
1997 J jnl
Am improved tail current source for low voltage applications.
IEEE J. Solid State Circuits
Fan You, Sherif H. K. Embabi, J. Francisco Duque-Carrillo, Edgar Sánchez-Sinencio
1997 J jnl
Cork quality classification system using a unified image processing and fuzzy-neural network methodology.
IEEE Trans. Neural Networks
Joongho Chang, Gunhee Han, José M. Valverde, Norman C. Griswold, J. Francisco Duque-Carrillo, Edgar Sánchez-Sinencio
1997 J jnl
Multistage amplifier topologies with nested G
IEEE J. Solid State Circuits
Fan You, Sherif H. K. Embabi, Edgar Sánchez-Sinencio
1997 J jnl
Programmable time-multiplexed switched-capacitor variable equalizer for arbitrary frequency response realizations.
IEEE J. Solid State Circuits
Raquel Pérez-Aloe, J. Francisco Duque-Carrillo, Edgar Sánchez-Sinencio, José M. Valverde, Guido Torelli, Alexander H. Reyes, Franco Maloberti
1996 A conf
A 1.5V class AB output buffer.
ISLPED
Fan You, Sherif H. K. Embabi, Edgar Sánchez-Sinencio
1996 — conf
A new method for wavelets generation.
EUSIPCO
Adrién Martínez-González, Laura Ortiz-Balbuena, Héctor M. Pérez Meana, Edgar Sánchez-Sinencio, Juan Carlos Sánchez-García
1996 J jnl
VERDI: an acoustically programmable and adjustable CMOS mixed-mode signal processor for hearing aid applications.
IEEE J. Solid State Circuits
J. Francisco Duque-Carrillo, Piero Malcovati, Franco Maloberti, Raquel Pérez-Aloe, Alexander H. Reyes, Edgar Sánchez-Sinencio, Guido Torelli, José M. Valverde
1995 C conf
A Design Scheme to Stabilize the Active Gain Enhancement Amplifier.
ISCAS
Fan You, Sherif H. K. Embabi, Edgar Sánchez-Sinencio, A. Ganesan
1995 C conf
A General Purpose Discrete-Time Multiplexing Neuron-Array Architecture.
ISCAS
Gunhee Han, Edgar Sánchez-Sinencio
1995 C conf
A Nonlinear Macromodel for CMOS OTAs.
ISCAS
Gabriel J. Gómez, Sherif H. K. Embabi, Edgar Sánchez-Sinencio, Martin C. Lefebvre
1995 C conf
A Universal Interface Between PC and Neural Networks Hardware.
ISCAS
Apollo Q. Fong, Ajay Kanji, Edgar Sánchez-Sinencio, José Pineda de Gyvez
1994 C conf
A Programmable 1.8-18MHz High-Q Fully-Differential Continuous-Time Filter with 1.5-2 Power Supply.
ISCAS
Joseph T. Nabicht, Edgar Sánchez-Sinencio, Jaime Ramírez-Angulo
1994 Misc conf
A power supply ramping and current measurement based technique for analog fault diagnosis.
VTS
Shyam S. Somayajula, Edgar Sánchez-Sinencio, José Pineda de Gyvez
1994 J jnl
Smart-pixel cellular neural networks in analog current-mode CMOS technology.
IEEE J. Solid State Circuits
Servando Espejo, Ángel Rodríguez-Vázquez, Rafael Domínguez-Castro, John L. Huertas, Edgar Sánchez-Sinencio
1994 C conf
Two Approaches for Current-Mode Filters using Voltage Follower and Transconductance Multipliers Building Blocks.
ISCAS
Jaime Ramírez-Angulo, Edgar Sánchez-Sinencio
1993 C conf
3v High-frequency Current-mode Filters.
ISCAS
Sterling L. Smith, Edgar Sánchez-Sinencio
1993 J jnl
A CMOS analog adaptive BAM with on-chip learning and weight refreshing.
IEEE Trans. Neural Networks
Bernabé Linares-Barranco, Edgar Sánchez-Sinencio, Ángel Rodríguez-Vázquez, José L. Huertas
1993 J jnl
A high-density and low-power charge-based Hamming network.
IEEE Trans. Very Large Scale Integr. Syst.
Yuping He, Ugur Çilingiroglu, Edgar Sánchez-Sinencio
1993 C conf
High Frequency Compensated Current-mode Ladder Filters Using Multiple Output OTAs.
ISCAS
Jaime Ramírez-Angulo, Edgar Sánchez-Sinencio
1993 C conf
Linearity, Accuracy and Bandwidth Considerations in Wideband CMOS Voltage Amplifiers.
ISCAS
Jaime Ramírez-Angulo, Roberto Sadkowski, Edgar Sánchez-Sinencio
1992 J jnl
A MOSFET-C variable equalizer circuit with simple on-chip automatic tuning.
IEEE J. Solid State Circuits
Satoshi Sakurai, Mohamnmed Ismail, Jean-Yves Michel, Edgar Sánchez-Sinencio, Robert Brannen
1992 J jnl
A modular CMOS design of a Hamming network.
IEEE Trans. Neural Networks
Moises E. Robinson, Hideki Yoneda, Edgar Sánchez-Sinencio
1992 J jnl
A modular T-mode design approach for analog neural network hardware implementations.
IEEE J. Solid State Circuits
Bernabé Linares-Barranco, Edgar Sánchez-Sinencio, Ángel Rodríguez-Vázquez, José L. Huertas
1992 J jnl
Analog neural programmable optimizers in CMOS VLSI technologies.
IEEE J. Solid State Circuits
Rafael Domínguez-Castro, Ángel Rodríguez-Vázquez, José Luis Huertas, Edgar Sánchez-Sinencio
1991 J jnl
A CMOS implementation of FitzHugh-Nagumo neuron model.
IEEE J. Solid State Circuits
Bernabé Linares-Barranco, Edgar Sánchez-Sinencio, Ángel Rodríguez-Vázquez, José L. Huertas
1991 Misc conf
CMOS Continuous BAM With On Chip Learning.
IWANN
Bernabé Linares-Barranco, Edgar Sánchez-Sinencio, Ángel Rodríguez-Vázquez, José Luis Huertas
1991 J jnl
CMOS OTA-C high-frequency sinusoidal oscillators.
IEEE J. Solid State Circuits
Bernabé Linares-Barranco, Ángel Rodríguez-Vázquez, Edgar Sánchez-Sinencio, José L. Huertas
1990 J jnl
Active compensation of operational transconductance amplifier filters using partial positive feedback.
IEEE J. Solid State Circuits
Jaime Ramírez-Angulo, Edgar Sánchez-Sinencio
1990 J jnl
Programmable switched-capacitor bump equalizer architecture.
IEEE J. Solid State Circuits
J. Francisco Duque-Carrillo, Jose Silva-Martinez, Edgar Sánchez-Sinencio
1989 J jnl
Operational transconductance amplifier-based nonlinear function syntheses.
IEEE J. Solid State Circuits
Edgar Sánchez-Sinencio, Jaime Ramírez-Angulo, Bernabé Linares-Barranco, Ángel Rodríguez-Vázquez
1985 J jnl
AROMA: An Area Optimized CAD Program for Cascade SC Filter Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Edgar Sánchez-Sinencio, Jaime Ramírez-Angulo
1973 — —
Computer-Aided Design of Microwave Circuits
Edgar Sánchez-Sinencio