Eddie Hung - RankMe

37 papers A 5B 9Misc 5Journal 11Unranked 7

Year	Rank	Type	Title / Venue / Authors
2025	B	`conf`	Compile in Seconds and Run on an FPGA with DynaRapid. FPL Andrea Guerrieri, Isaac John Wetenkamp, Chris Lavin, Eddie Hung, Lana Josipovic, Paolo Ienne
2024	B	`conf`	DynaRapid: Fast-Tracking from C to Routed Circuits. FPL Andrea Guerrieri, Srijeet Guha, Chris Lavin, Eddie Hung, Lana Josipovic, Paolo Ienne
2023	A	`conf`	Invited Paper: RapidWright: Unleashing the Full Power of FPGA Technology with Domain-Specific Tooling. ICCAD Chris Lavin, Eddie Hung
2023	A	`conf`	Narrowing the Synthesis Gap: Academic FPGA Synthesis is Catching Up With the Industry. DATE Benjamin Lukas Cajus Barzen, Arya Reais-Parsi, Eddie Hung, Minwoo Kang, Alan Mishchenko, Jonathan W. Greene, John Wawrzynek
2023	J	`jnl`	RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration. ACM Trans. Reconfigurable Technol. Syst. Licheng Guo, Pongstorn Maidee, Yun Zhou, Chris Lavin, Eddie Hung, Wuxi Li, Jason Lau, Weikang Qiao, Yuze Chi, Linghao Song, Yuanlong Xiao, Alireza Kaviani, Zhiru Zhang, Jason Cong
2022	—	`conf`	100% Visibility at MHz Speed: Efficient Soft Scan-Chain Insertion on AMD/Xilinx FPGAs. ARC Hossein Omidian, Eddie Hung, Dinesh Gaitonde
2019	Misc	`conf`	EFCAD - An Embedded FPGA CAD Tool Flow for Enabling On-chip Self-Compilation. FCCM Khoa Dang Pham, Malte Vesper, Dirk Koch, Eddie Hung
2019	Misc	`conf`	Yosys+nextpnr: An Open Source Framework from Verilog to Bitstream for Commercial FPGAs. FCCM David Shah, Eddie Hung, Clifford Wolf, Serge Bazanski, Dan Gisselquist, Miodrag Milanovic
2019	J	`jnl`	Yosys+nextpnr: an Open Source Framework from Verilog to Bitstream for Commercial FPGAs. CoRR David Shah, Eddie Hung, Clifford Wolf, Serge Bazanski, Dan Gisselquist, Miodrag Milanovic
2018	B	`conf`	Extending post-silicon coverage measurement using time-multiplexed FPGA overlays. ETS Fatemeh Eslami, Eddie Hung, Steven J. E. Wilton
2018	J	`jnl`	KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs. ACM Trans. Reconfigurable Technol. Syst. James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides
2018	—	`conf`	KOCL: Kernel-level Power Estimation for Arbitrary FPGA-SoC-accelerated OpenCL Applications. IWOCL James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides
2017	J	`jnl`	KOCL: Power Self- Awareness for Arbitrary FPGA-SoC-Accelerated OpenCL Applications. IEEE Des. Test James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides
2017	B	`conf`	STRIPE: Signal selection for runtime power estimation. FPL James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides
2017	J	`jnl`	Transparent In-Circuit Assertions for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Eddie Hung, Tim Todman, Wayne Luk
2016	J	`jnl`	Enabling Effective FPGA Debug using Overlays: Opportunities and Challenges. CoRR Fatemeh Eslami, Eddie Hung, Steven J. E. Wilton
2016	Misc	`conf`	KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs. FCCM Eddie Hung, James J. Davis, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides
2016	A	`conf`	Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only). FPGA James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides
2015	Misc	`conf`	Accelerating SpMV on FPGAs by Compressing Nonzero Values. FCCM Paul Grigoras, Pavel Burovskiy, Eddie Hung, Wayne Luk
2015	A	`conf`	Delay-Bounded Routing for Shadow Registers. FPGA Eddie Hung, Joshua M. Levine, Edward A. Stott, George A. Constantinides, Wayne Luk
2015	B	`conf`	Mind the (synthesis) gap: Examining where academic FPGA tools lag behind industry. FPL Eddie Hung
2014	J	`jnl`	Accelerating FPGA debug: Increasing visibility using a runtime reconfigurable observation and triggering network. ACM Trans. Design Autom. Electr. Syst. Eddie Hung, Steven J. E. Wilton
2014	—	`conf`	Faster FPGA Debug: Efficiently Coupling Trace Instruments with User Circuitry. ARC Eddie Hung, Jeffrey B. Goeders, Steven J. E. Wilton
2014	J	`jnl`	Incremental Trace-Buffer Insertion for FPGA Debug. IEEE Trans. Very Large Scale Integr. Syst. Eddie Hung, Steven J. E. Wilton
2014	B	`conf`	Transparent insertion of latency-oblivious logic onto FPGAs. FPL Eddie Hung, Tim Todman, Wayne Luk
2013	Misc	`conf`	Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices. FCCM Eddie Hung, Fatemeh Eslami, Steven J. E. Wilton
2013	J	`jnl`	Linking the Verification and Validation of Complex Integrated Circuits Through Shared Coverage Metrics. IEEE Des. Test Eddie Hung, Bradley R. Quinton, Steven J. E. Wilton
2013	—	`conf`	Maximum flow algorithms for maximum observability during FPGA debug. FPT Eddie Hung, Al-Shahna Jamal, Steven J. E. Wilton
2013	J	`jnl`	Scalable Signal Selection for Post-Silicon Debug. IEEE Trans. Very Large Scale Integr. Syst. Eddie Hung, Steven J. E. Wilton
2013	A	`conf`	Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers. FPGA Eddie Hung, Steven J. E. Wilton
2012	J	`jnl`	Cogeneration of Fast Motion Estimation Processors and Algorithms for Advanced Video Coding. IEEE Trans. Very Large Scale Integr. Syst. José Luis Núñez-Yáñez, Atukem Nabina, Eddie Hung, George Vafiadis
2012	B	`conf`	Limitations of incremental signal-tracing for FPGA debug. FPL Eddie Hung, Steven J. E. Wilton
2012	—	`conf`	Rapid RTL-based signal ranking for FPGA prototyping. FPT Steven J. E. Wilton, Bradley R. Quinton, Eddie Hung
2011	—	`conf`	On evaluating signal selection algorithms for post-silicon debug. ISQED Eddie Hung, Steven J. E. Wilton
2011	B	`conf`	Speculative Debug Insertion for FPGAs. FPL Eddie Hung, Steven J. E. Wilton
2009	—	`conf`	A detailed delay path model for FPGAs. FPT Eddie Hung, Steven J. E. Wilton, Haile Yu, Thomas C. P. Chau, Philip Heng Wai Leong
2008	B	`conf`	A configurable and programmable motion estimation processor for the H.264 video codec. FPL José Luis Núñez-Yáñez, Eddie Hung, Vassilios A. Chouliaras