Ed van Tuijl

19 papers Journal 5Unranked 14
YearRankTypeTitle / Venue / Authors
2017 — conf
Range pre-selection sampling technique to reduce input drive energy for SAR ADCs.
A-SSCC
Harijot Singh Bindra, Joeri Lechevallier, Anne-Johan Annema, Simon M. Louwsma, Ed van Tuijl, Bram Nauta
2015 — conf
15.3 A 115dB-DR audio DAC with -61dBFS out-of-band noise.
ISSCC
Hugo Westerveld, Daniël Schinkel, Ed van Tuijl
2015 — conf
Session 5 overview: Analog techniques: Analog subcommittee.
ISSCC
Xicheng Jiang, Ed van Tuijl
2011 — conf
A narrow-to-wideband scrambling technique increasing software radio receiver linearity.
ESSCIRC
Fabian van Houwelingen, Ed van Tuijl, Bram Nauta, Maarten Vertregt
2010 J jnl
A 10-bit Charge-Redistribution ADC Consuming 1.9 μ W at 1 MS/s.
IEEE J. Solid State Circuits
Michiel van Elzakker, Ed van Tuijl, Paul F. J. Geraedts, Daniël Schinkel, Eric A. M. Klumperink, Bram Nauta
2010 J jnl
Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects.
IEEE J. Solid State Circuits
Eisse Mensink, Daniël Schinkel, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta
2009 J jnl
Low-Power, High-Speed Transceivers for Network-on-Chip Communication.
IEEE Trans. Very Large Scale Integr. Syst.
Daniël Schinkel, Eisse Mensink, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta
2008 — conf
A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC.
ISSCC
Michiel van Elzakker, Ed van Tuijl, Paul F. J. Geraedts, Daniël Schinkel, Eric A. M. Klumperink, Bram Nauta
2008 — conf
A 90μW 12MHz Relaxation Oscillator with a -162dB FOM.
ISSCC
Paul F. J. Geraedts, Ed van Tuijl, Eric A. M. Klumperink, Gerard Wienk, Bram Nauta
2008 — conf
Audio at low and high power.
ESSCIRC
Marco Berkhout, Lucien J. Breems, Ed van Tuijl
2008 — conf
Session 20 - Advanced wireline techniques.
CICC
Ed van Tuijl, Ken Chang
2007 — conf
A 0.28pJ/b 2Gb/s/ch Transceiver in 90nm CMOS for 10mm On-Chip interconnects.
ISSCC
Eisse Mensink, Daniël Schinkel, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta
2007 — conf
A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time.
ISSCC
Daniël Schinkel, Eisse Mensink, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta
2007 — conf
A Time-Interleaved Track & hold in 0.13 μm CMOS sub-sampling a 4 GHz signal with 43 dB SNDR.
CICC
Simon M. Louwsma, Ed van Tuijl, Maarten Vertregt, Bram Nauta
2007 J jnl
Optimal Positions of Twists in Global On-Chip Differential Interconnects.
IEEE Trans. Very Large Scale Integr. Syst.
Eisse Mensink, Daniël Schinkel, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta
2005 — conf
An audio FIR-DAC in a BCD process for high power class-D amplifiers.
ESSCIRC
T. S. Doorn, Ed van Tuijl, Daniël Schinkel, Anne-Johan Annema, Marco Berkhout, Bram Nauta
2005 — conf
Optimally-placed twists in global on-chip differential interconnects.
ESSCIRC
Eisse Mensink, Daniël Schinkel, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta
2004 — conf
Reducing quantization noise with recursive Sigma Delta modulators.
ISCAS (1)
Daniël Schinkel, Ed van Tuijl, Anne-Johan Annema
2002 J jnl
A coupled sawtooth oscillator combining low jitter with high control linearity.
IEEE J. Solid State Circuits
Sander L. J. Gierkink, Ed van Tuijl