Ed F. Deprettere

135 papers A* 3A 3B 5C 8Misc 24Journal 41Unranked 45

Year	Rank	Type	Title / Venue / Authors
2013	—	`ch.`	Dynamic Dataflow Graphs. Handbook of Signal Processing Systems Shuvra S. Bhattacharyya, Ed F. Deprettere, Bart D. Theelen
2013	—	`book`	Handbook of Signal Processing Systems Handbook of Signal Processing Systems Shuvra S. Bhattacharyya, Ed F. Deprettere, Rainer Leupers, Jarmo Takala
2013	—	`ch.`	Multidimensional Dataflow Graphs. Handbook of Signal Processing Systems Joachim Keinert, Ed F. Deprettere
2012	—	`conf`	Special session on "aspects of Cyber-Physical Systems". ICSAMOS Ed F. Deprettere
2011	—	`conf`	USHA: Unified software and hardware architecture for video decoding. SASP Adarsha Rao, S. K. Nandy, Hristo Nikolov, Ed F. Deprettere
2010	C	`ed.`	13th International Workshop on Software and Compilers for Embedded Systems, SCOPES '10, St. Goar, Germany, June 29-30, 2010 SCOPES Ed F. Deprettere, Todor P. Stefanov
2010	—	`ch.`	Dynamic and Multidimensional Dataflow Graphs. Handbook of Signal Processing Systems Shuvra S. Bhattacharyya, Ed F. Deprettere, Joachim Keinert
2010	—	`book`	Handbook of Signal Processing Systems Shuvra S. Bhattacharyya, Ed F. Deprettere, Rainer Leupers, Jarmo Takala
2009	—	`conf`	Introduction to Mastering Cell BE and GPU Execution Platforms. SAMOS Ed F. Deprettere, Ana Lucia Varbanescu
2009	—	`conf`	Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell. SAMOS Dmitry Nadezhkin, Sjoerd Meijer, Todor P. Stefanov, Ed F. Deprettere
2008	J	`jnl`	Automated Integration of Dedicated Hardwired IP Cores in Heterogeneous MPSoCs Designed with ESPAM. EURASIP J. Embed. Syst. Hristo Nikolov, Todor P. Stefanov, Ed F. Deprettere
2008	A*	`conf`	Daedalus: toward composable multimedia MP-SoC design. DAC Hristo Nikolov, Mark Thompson, Todor P. Stefanov, Andy D. Pimentel, Simon Polstra, Raj Bose, Claudiu Zissulescu, Ed F. Deprettere
2008	J	`jnl`	Deriving efficient control in Process Networks with Compaan/Laura. Int. J. Embed. Syst. Steven Derrien, Alexandru Turjan, Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere
2008	—	`conf`	Hierarchical run time deadlock detection in process networks. SiPS Bin Jiang, Ed F. Deprettere, Bart Kienhuis
2008	J	`jnl`	Systematic and Automated Multiprocessor System Design, Programming, and Implementation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hristo Nikolov, Todor P. Stefanov, Ed F. Deprettere
2008	—	`conf`	Tool Integration and Interoperability Challenges of a System-Level Design Flow: A Case Study. SAMOS Andy D. Pimentel, Todor P. Stefanov, Hristo Nikolov, Mark Thompson, Simon Polstra, Ed F. Deprettere
2007	Misc	`conf`	A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs. CODES+ISSS Mark Thompson, Hristo Nikolov, Todor P. Stefanov, Andy D. Pimentel, Cagkan Erbas, Simon Polstra, Ed F. Deprettere
2007	J	`jnl`	Classifying interprocess communication in process network representation of nested-loop programs. ACM Trans. Embed. Comput. Syst. Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
2007	B	`conf`	Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips. FPL Hristo Nikolov, Todor P. Stefanov, Ed F. Deprettere
2007	J	`jnl`	Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation. IEEE Trans. Signal Process. Ming-Yung Ko, Claudiu Zissulescu, Sebastian Puthenpurayil, Shuvra S. Bhattacharyya, Bart Kienhuis, Ed F. Deprettere
2007	J	`jnl`	Transforming Signal Processing Applications into Parallel Implementations. EURASIP J. Adv. Signal Process. Ed F. Deprettere, Roger F. Woods, Ingrid Verbauwhede, Erwin A. de Kock
2006	—	`conf`	Affine Nested Loop Programs and their Binary Parameterized Dataflow Graph Counterparts. ASAP Ed F. Deprettere, Todor P. Stefanov, Shuvra S. Bhattacharyya, Mainak Sen
2006	B	`conf`	Efficient Automated Synthesis, Programing, and Implementation of Multi-Processor Platforms on FPGA Chips. FPL Hristo Nikolov, Todor P. Stefanov, Ed F. Deprettere
2006	—	`conf`	FPGA Implementation of a Prototype Hierarchical Control Network for Large-Scale Signal Processing Applications. Euro-Par Jérôme Lemaitre, Ed F. Deprettere
2006	Misc	`conf`	Multi-processor system design with ESPAM. CODES+ISSS Hristo Nikolov, Todor P. Stefanov, Ed F. Deprettere
2006	J	`jnl`	Requirements for Interfacing IP-Components in Re-configurable Platforms. J. VLSI Signal Process. Jérôme Lemaitre, Sylvain Alliot, Ed F. Deprettere
2005	—	`conf`	Behavioral specification of control interface for signal processing applications. ASAP Jérôme Lemaitre, Sylvain Alliot, Ed F. Deprettere
2005	B	`conf`	Communication Synthesis in a multiprocessor environment. FPL Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere
2005	—	`conf`	Expression Synthesis in Process Networks generated by LAURA. ASAP Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere
2005	—	`conf`	FPL-3E: Towards Language Support for Reconfigurable Packet Processing. SAMOS Mihai-Lucian Cristea, Claudiu Zissulescu, Ed F. Deprettere, Herbert Bos
2005	Misc	`conf`	Modeling and FPGA Implementation of Applications Using Parameterized Process Networks with Non-Static Parameters. FCCM Hristo Nikolov, Todor P. Stefanov, Ed F. Deprettere
2005	J	`jnl`	Solving Out-of-Order Communication in Kahn Process Networks. J. VLSI Signal Process. Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
2004	—	`conf`	A Hierarchical Classification Scheme to Derive Interprocess Communication in Process Networks. ASAP Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
2004	C	`conf`	An Integer Linear Programming Approach to Classify the Communication in Process Networks. SCOPES Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
2004	C	`conf`	Architecture Exploration of a Large Scale System. IEEE International Workshop on Rapid System Prototyping Sylvain Alliot, Ed F. Deprettere
2004	—	`conf`	Communication Optimization in Compaan Process Networks. SAMOS Ioan Cimpian, Alexandru Turjan, Ed F. Deprettere, Erwin A. de Kock
2004	—	`conf`	Constraints Derivation and Propagation for Large-Scale Embedded Systems Exploration. SAMOS Laurentiu Nicolae, Ed F. Deprettere
2004	B	`conf`	Increasing Pipelined IP Core Utilization in Process Networks Using Exploration. FPL Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere
2004	—	`conf`	On the (Re-)Use of IP-Components in Re-configurable Platforms. SAMOS Jérôme Lemaitre, Sylvain Alliot, Ed F. Deprettere
2004	A	`conf`	System Design Using Kahn Process Networks: The Compaan/Laura Approach. DATE Todor P. Stefanov, Claudiu Zissulescu, Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
2004	Misc	`conf`	Translating affine nested-loop programs to process networks. CASES Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
2003	J	`jnl`	Analysis of joint angle-frequency estimation using ESPRIT. IEEE Trans. Signal Process. Aweke N. Lemma, Alle-Jan van der Veen, Ed F. Deprettere
2003	—	`conf`	Context-Aware Process Networks. ASAP Hylke W. van Dijk, Henk J. Sips, Ed F. Deprettere
2003	Misc	`conf`	Deriving process networks from weakly dynamic applications in system-level design. CODES+ISSS Todor P. Stefanov, Ed F. Deprettere
2003	A	`conf`	Fast and Accurate Multiprocessor Architecture Exploration with Symbolic Programs. DATE Vladimir D. Zivkovic, Erwin A. de Kock, Pieter van der Wolf, Ed F. Deprettere
2003	B	`conf`	Laura: Leiden Architecture Research and Exploration Tool. FPL Claudiu Zissulescu, Todor P. Stefanov, Bart Kienhuis, Ed F. Deprettere
2003	J	`jnl`	Modeling Stream-Based Applications Using the SBF Model of Computation. J. VLSI Signal Process. Bart Kienhuis, Ed F. Deprettere
2002	—	`conf`	A Compile Time Based Approach for Solving Out-of-Order Communication in Kahn Process Networks. ASAP Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
2002	—	`conf`	A Methodology to Design Programmable Embedded Systems - The Y-Chart Approach. Embedded Processor Design Challenges Bart Kienhuis, Ed F. Deprettere, Pieter van der Wolf, Kees A. Vissers
2002	—	`conf`	Algorithmic transformation techniques for efficient exploration of alternative application instances. CODES Todor P. Stefanov, Bart Kienhuis, Ed F. Deprettere
2002	J	`jnl`	Compilation From Matlab to Process Networks Realized in FPGA. Des. Autom. Embed. Syst. Tim Harriss, Richard L. Walke, Bart Kienhuis, Ed F. Deprettere
2002	—	`ed.`	Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS Embedded Processor Design Challenges Ed F. Deprettere, Jürgen Teich, Stamatis Vassiliadis
2002	J	`jnl`	Preface. Des. Autom. Embed. Syst. Ed F. Deprettere, Bart Kienhuis, Richard L. Walke
2002	—	`conf`	Translating Imperative Affine Nested Loop Programs into Process Networks. Embedded Processor Design Challenges Ed F. Deprettere, Edwin Rijpkema, Bart Kienhuis
2001	J	`jnl`	A Methodology for Architecture Exploration of Heterogeneous Signal Processing Systems. J. VLSI Signal Process. Paul Lieverse, Pieter van der Wolf, Kees A. Vissers, Ed F. Deprettere
2001	—	`conf`	A trace transformation technique for communication refinement. CODES Paul Lieverse, Pieter van der Wolf, Ed F. Deprettere
2001	J	`jnl`	A unified algebraic transformation approach for parallel recursive and adaptive filtering and SVD algorithms. IEEE Trans. Signal Process. Jun Ma, Keshab K. Parhi, Ed F. Deprettere
2001	J	`jnl`	Exploring Embedded-Systems Architectures with Artemis. Computer Andy D. Pimentel, Louis O. Hertzberger, Paul Lieverse, Pieter van der Wolf, Ed F. Deprettere
2001	A	`conf`	System Level Design with Spade: an M-JPEG Case Study. ICCAD Paul Lieverse, Todor P. Stefanov, Pieter van der Wolf, Ed F. Deprettere
2000	J	`jnl`	A Floating Point Vectoring Algorithm Based on Fast Rotations. J. VLSI Signal Process. Kees-Jan van der Kolk, Jeong-A Lee, Ed F. Deprettere
2000	Misc	`conf`	Analysis of ESPRIT based joint angle-frequency estimation. ICASSP Aweke N. Lemma, Alle-Jan van der Veen, Ed F. Deprettere
2000	J	`jnl`	Annihilation-reordering look-ahead pipelined CORDIC-based RLS adaptive filters and their application to adaptive beamforming. IEEE Trans. Signal Process. Jun Ma, Keshab K. Parhi, Ed F. Deprettere
2000	—	`conf`	Compaan: deriving process networks from Matlab for embedded signal processing architectures. CODES Bart Kienhuis, Edwin Rijpkema, Ed F. Deprettere
2000	J	`jnl`	Deriving Process Networks from Nested Loop Algorithms. Parallel Process. Lett. Edwin Rijpkema, Ed F. Deprettere, Bart Kienhuis
2000	J	`jnl`	Efficient implementations of pipelined CORDIC based IIR digital filters using fast orthonormal μ-rotations. IEEE Trans. Signal Process. Jun Ma, Keshab K. Parhi, Gerben J. Hekstra, Ed F. Deprettere
2000	J	`jnl`	Guest Editor's Introduction. J. VLSI Signal Process. Gerben J. Hekstra, Ed F. Deprettere, Jeong-A Lee
2000	—	`conf`	High Level Modeling for Parallel Executions of Nested Loop Algorithms. ASAP Ed F. Deprettere, Edwin Rijpkema, Paul Lieverse, Bart Kienhuis
1999	J	`jnl`	A Clustering Approach to Explore Grain-Sizes in the Definition of Processing Elements in Dataflow Architectures. J. VLSI Signal Process. Paul Lieverse, Ed F. Deprettere, Bart Kienhuis, Erwin A. de Kock
1999	—	`conf`	A Floating Point Vectoring Algorithm Based on Fast Rotations. EUROMICRO Kees-Jan van der Kolk, Ed F. Deprettere, Jeong-A Lee
1999	—	`conf`	Derivation of parallel and pipelined orthogonal filter architectures via algorithm transformations. ISCAS (3) Jun Ma, Keshab K. Parhi, Ed F. Deprettere
1999	J	`jnl`	Multiresolution ESPRIT algorithm. IEEE Trans. Signal Process. Aweke N. Lemma, Alle-Jan van der Veen, Ed F. Deprettere
1999	C	`ed.`	Third IEEE Workshop on Multimedia Signal Processing, MMSP 1999, Copenhagen, Denmark, September 13-15, 1999 MMSP K. J. Ray Liu, Jörn Ostermann, Ed F. Deprettere, W. Bastiaan Kleijn, John Aasted Sørensen
1998	J	`jnl`	Efficient Partitioning of Algorithms for Long Convolutions and their Mapping onto Architectures. J. VLSI Signal Process. Laurens Bierens, Ed F. Deprettere
1998	Misc	`conf`	Joint angle-frequency estimation using multi-resolution ESPRIT. ICASSP Aweke N. Lemma, Alle-Jan van der Veen, Ed F. Deprettere
1998	Misc	`conf`	Pipelined CORDIC based QRD-MVDR adaptive beamforming. ICASSP Jun Ma, Keshab K. Parhi, Ed F. Deprettere
1998	Misc	`conf`	Robust exponential modeling of audio signals. ICASSP Joost Nieuwenhuijse, Richard Heusdens, Ed F. Deprettere
1998	—	`conf`	The construction of a retargetable simulator for an architecture template. CODES Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, Pieter van der Wolf
1998	—	`conf`	Waveform interpolation coding with pitch-spaced subbands. ICSLP W. Bastiaan Kleijn, Huimin Yang, Ed F. Deprettere
1997	—	`conf`	A strategy for determining a Jacobi specific dataflow processor. ASAP Edwin Rijpkema, Gerben J. Hekstra, Ed F. Deprettere, Jun Ma
1997	—	`conf`	An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures. ASAP Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, Pieter van der Wolf
1997	C	`conf`	Fast Rotations: Low-cost Arithmetic Methods for Orthonormal Rotation. IEEE Symposium on Computer Arithmetic Gerben J. Hekstra, Ed F. Deprettere
1997	Misc	`conf`	Perceptual entropy rate estimates for the phonemes of American English. ICASSP Vincent van de Laar, W. Bastiaan Kleijn, Ed F. Deprettere
1997	Misc	`conf`	Pipelining of cordic based IIR digital filters. ICASSP Jun Ma, Keshab K. Parhi, Ed F. Deprettere
1997	—	`conf`	Quantization using wavelet based temporal decomposition of the LSF. EUROSPEECH Aweke N. Lemma, W. Bastiaan Kleijn, Ed F. Deprettere
1996	J	`jnl`	A fully pipelined RLS-based array for channel equalization. J. VLSI Signal Process. Marc Moonen, Ed F. Deprettere
1996	Misc	`conf`	Engineering multirate convolutions for radar imaging. ICASSP Laurens Bierens, Ed F. Deprettere
1996	—	`conf`	Jacobi-Specific Processor Arrays. ASAP Hylke W. van Dijk, Gerben J. Hekstra, Ed F. Deprettere
1996	—	`conf`	State space behavior in time-varying biorthogonal filter banks. EUSIPCO Aweke N. Lemma, Ed F. Deprettere
1996	J	`jnl`	Two-sided controlled transition in biorthogonal time-varying filter banks. IEEE Signal Process. Lett. Aweke N. Lemma, Ed F. Deprettere
1995	J	`jnl`	A parallel image-rendering algorithm and architecture based on ray tracing and radiosity shading. Comput. Graph. Li-Sheng Shen, Ed F. Deprettere, Patrick M. Dewilde
1995	Misc	`conf`	On the derivation of parallel filter structures for adaptive eigenvalue and singular value decompositions. ICASSP Marc Moonen, Ed F. Deprettere, Ian K. Proudler, John G. McWhirter
1995	J	`jnl`	Scalable parallel processor array for Jacobi-type matrix computations. Integr. Hylke W. van Dijk, Gerben J. Hekstra, Ed F. Deprettere
1994	—	`conf`	A 'Jacobi' signal processing unit for time-adaptive SVD. ICASSP (2) Ed F. Deprettere, Hylke W. van Dijk, Gerben J. Hekstra
1994	—	`conf`	A parallel system for photo realistic artificial scene rendering. ASAP Ed F. Deprettere, Gerben J. Hekstra, Li-Sheng Shen, Jichun Bu, Gerrit Boersma
1994	J	`jnl`	Direction finding of multiple wide-band emitters using state-space modeling. Signal Process. Filiep Vanpoucke, Marc Moonen, Ed F. Deprettere
1994	C	`conf`	Is it Possible to achieve a Teraflop/s on a chip? From High Performance Algorithms to Architectures. ISCAS Francky Catthoor, Ed F. Deprettere, Yu Hen Hu, Jan M. Rabaey, Heinrich Meyr, Lothar Thiele
1994	J	`jnl`	Parallel and adaptive high-resolution direction finding. IEEE Trans. Signal Process. Marc Moonen, Filiep J. Vanpoucke, Ed F. Deprettere
1993	J	`jnl`	Example of combined algorithm development and architecture design. Integr. Ed F. Deprettere
1993	C	`conf`	Floating point Cordic. IEEE Symposium on Computer Arithmetic Gerben J. Hekstra, Ed F. Deprettere
1993	—	`conf`	Subband filtering: Cordic modulation and systolic quadrature mirror filter tree. ASAP Ed F. Deprettere, Richard Heusdens, Hendrik Theunis
1993	J	`jnl`	Subspace-based signal analysis using singular value decomposition. Proc. IEEE Alle-Jan van der Veen, Ed F. Deprettere, A. Lee Swindlehurst
1992	—	`conf`	A Parallel-Pipelined Multiprocessor System for the Radiosity Method. Eurographics Workshop on Graphics Hardware Li-Sheng Shen, Ed F. Deprettere
1992	J	`jnl`	Azimuth and elevation computation in high resolution DOA estimation. IEEE Trans. Signal Process. Alle-Jan van der Veen, P. Bas Ober, Ed F. Deprettere
1992	—	`conf`	Parallel architecture for a pel-recursive motion estimation algorithm. ASAP Emmanuel D. Frimout, Johannes N. Driessen, Ed F. Deprettere
1992	J	`jnl`	Parallel architecture for a pel-recursive motion estimation algorithm. IEEE Trans. Circuits Syst. Video Technol. Emmanuel D. Frimout, Johannes N. Driessen, Ed F. Deprettere
1991	—	`conf`	A hardware design system based on object-oriented principles. EURO-DAC A. J. van der Hoeven, Ed F. Deprettere, P. van Prooijen, Patrick M. Dewilde
1991	C	`conf`	Design and implementation of a floating-point quasi-systolic general purpose CORDIC rotator for high-rate parallel data and signal processing. IEEE Symposium on Computer Arithmetic Alfons A. J. de Lange, Ed F. Deprettere
1991	Misc	`conf`	Efficient methods to compute azimuth and elevation in high resolution DOA estimation. ICASSP P. Bas Ober, Ed F. Deprettere, Alle-Jan van der Veen
1991	J	`jnl`	Introduction. J. VLSI Signal Process. Ed F. Deprettere
1991	J	`jnl`	Parallel VLSI matrix pencil algorithm for high resolution direction finding. IEEE Trans. Signal Process. Alle-Jan van der Veen, Ed F. Deprettere
1991	—	`conf`	Processor clustering for the design of optimal fixed-size systolic arrays. ASAP Jichun Bu, Ed F. Deprettere
1991	—	`conf`	Space Partitioning for Mapping Radiosity Computations onto a Pipelined Parallel Architecture (II). Advances in Computer Graphics Hardware (Machines) Li-Sheng Shen, F. A. J. Laarakker, Ed F. Deprettere
1990	—	`conf`	A New Space Partitioning for Mapping Computations of the Radiosity Method onto a Highly Pipelined Parallel Architecture. Advances in Computer Graphics Hardware V Li-Sheng Shen, Ed F. Deprettere, Patrick M. Dewilde
1990	—	`conf`	A design methodology for fixed-size systolic arrays. ASAP Jichun Bu, Ed F. Deprettere, Patrick M. Dewilde
1990	J	`jnl`	A model for the high-level description and simulation of VLSI networks. IEEE Micro A. J. van der Hoeven, Alfons A. J. de Lange, Ed F. Deprettere, Patrick M. Dewilde
1990	Misc	`conf`	Real time application of the floating point pipeline CORDIC processor in massive-parallel pipelined DSP algorithms. ICASSP Alfons A. J. de Lange, Ed F. Deprettere, Alle-Jan van der Veen, Jichun Bu
1990	—	`conf`	Systolic array implementation of nested loop programs. ASAP Jichun Bu, Ed F. Deprettere, Lothar Thiele
1989	—	`conf`	A Hardware Algorithm for Fast Realistic Image Synthesis. Advances in Computer Graphics Hardware A. C. Yilmaz, S. Hagestein, Ed F. Deprettere, Patrick M. Dewilde
1989	A*	`conf`	A New Model for the High Level Description and Simulation of VLSI Networks. DAC A. J. van der Hoeven, A. A. de Lange, Ed F. Deprettere, Patrick M. Dewilde
1989	J	`jnl`	A VLSI system architecture for high-speed radiative transfer 3D image synthesis. Vis. Comput. Jichun Bu, Ed F. Deprettere
1989	J	`jnl`	A systolic algorithm and architecture for solving sets of linear equations with multi-band coefficient matrix. J. VLSI Signal Process. Paul F. C. Krekel, Ed F. Deprettere
1988	J	`jnl`	A class of analysis-by-synthesis predictive coders for high quality speech coding at rates between 4.8 and 16 kbit/s. IEEE J. Sel. Areas Commun. Peter Kroon, Ed F. Deprettere
1988	Misc	`conf`	Converting sequential iterative algorithms to recurrent equations for automatic design of systolic arrays. ICASSP Jichun Bu, Ed F. Deprettere
1988	A*	`conf`	Design of a Concurrent Computer for Solving Systems of Linear Equations. ISCA Kishan Jainandunsing, Ed F. Deprettere
1987	—	`conf`	A VLSI System Architecture for High-Speed Radiative Transfer 3D Image Synthesis. Eurographics Jichun Bu, Ed F. Deprettere
1987	Misc	`conf`	Multi-pulse and regular-pulse LP coding of images. ICASSP Caspar Horne, Ed F. Deprettere
1986	Misc	`conf`	A low complexity regular pulse coding scheme with a reduced transmission delay. ICASSP Peter Kroon, Robert J. Sluyter, Ed F. Deprettere
1986	J	`jnl`	Design and VLSI Implementation of a Concurrent Solver for N-Coupled Least-Squares Fitting Problems. IEEE J. Sel. Areas Commun. Kishan Jainandunsing, Ed F. Deprettere
1986	J	`jnl`	Regular-pulse excitation-A novel approach to effective and efficient multipulse coding of speech. IEEE Trans. Acoust. Speech Signal Process. Peter Kroon, Ed F. Deprettere, Robert J. Sluyter
1985	Misc	`conf`	Design and VLSI implementation of a concurrent solver for N coupled least-squares fitting problems. ICASSP Ed F. Deprettere, Kishan Jainandunsing
1985	Misc	`conf`	Regular excitation reduction for effective and efficient LP-coding of speech. ICASSP Ed F. Deprettere, Peter Kroon
1984	Misc	`conf`	Experimental evaluation of different approaches to the multi-pulse coder. ICASSP Peter Kroon, Ed F. Deprettere
1984	Misc	`conf`	Pipelined cordic architectures for fast VLSI filtering and array processing. ICASSP Ed F. Deprettere, Patrick M. Dewilde, R. Udo
1983	Misc	`conf`	Synthesis and fixed-point implementation of pipelined true orthogonal filters. ICASSP Ed F. Deprettere
1982	Misc	`conf`	Fast non-stationary lattice recursions for adaptive modeling and estimation. ICASSP Ed F. Deprettere