Eby G. Friedman

321 papers A* 10A 7C 63Journal 133Unranked 106
YearRankTypeTitle / Venue / Authors
2026 J jnl
Inductorless dynamic logic based on 2 ϕ -Josephson junctions.
Integr.
Ana Mitrovic, Eby G. Friedman
2025 J jnl
High Efficiency Multiply-Accumulator Using Ternary Logic and Ternary Approximate Algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap.
Wanting Wen, Guangchao Zhao, Wanbo Hu, Ziye Li, Xingli Wang, Eby G. Friedman, Beng Kang Tay, Shaolin Ke, Mingqiang Huang
2025 C conf
Network-on-Interposer Co-Design for Heterogeneous Chiplet-Based Integrated Systems.
ISCAS
Andres Ayes, Eby G. Friedman, Marilyn Wolf
2025 C conf
Partitioning SFQ Circuits for Serial Biasing in Heterogeneous Circuits.
ISCAS
Tejumadejesu Oluwadamilare, Eby G. Friedman
2024 J jnl
Efficient Ternary Logic Circuits Optimized by Ternary Arithmetic Algorithms.
IEEE Trans. Emerg. Top. Comput.
Guangchao Zhao, Zhiwei Zeng, Xingli Wang, Abdelrahman G. Qoutb, Philippe Coquet, Eby G. Friedman, Beng Kang Tay, Mingqiang Huang
2024 J jnl
Harnessing stochasticity for superconductive multi-layer spike-rate-coded neuromorphic networks.
Neuromorph. Comput. Eng.
Alexander J. Edwards, Gleb Krylov, Joseph S. Friedman, Eby G. Friedman
2024 J jnl
Power Aware Placement of On-Chip Voltage Regulators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rassul Bairamkulov, Eby G. Friedman
2024 J jnl
Quasi-Adiabatic Clock Networks in 3-D Voltage Stacked Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Andres Ayes, Eby G. Friedman
2024 J jnl
Test Modules for Enhanced Testability of Single Flux Quantum Integrated Circuits.
J. Electron. Test.
Abdelrahman G. Qoutb, Jamil Kawa, Eby G. Friedman
2024 J jnl
Thermal Exploration of RSFQ Integrated Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Ana Mitrovic, Eby G. Friedman
2023 J jnl
Deep Neuromorphic Networks with Superconducting Single Flux Quanta.
CoRR
Gleb Krylov, Alexander J. Edwards, Joseph S. Friedman, Eby G. Friedman
2023 J jnl
Double magnetic tunnel junction two bit memory and nonvolatile logic for
Microelectron. J.
Abdelrahman G. Qoutb, Eby G. Friedman
2023 — conf
Dual Sawtooth-Based Delay Locked Loops for Heterogeneous 3-D Clock Networks.
SOCC
Andres Ayes, Eby G. Friedman
2023 J jnl
Linear Clock Tree Topology for Dynamic Source Synchronous and Fully Synchronous 3-D Interfaces.
Integr.
Andres Ayes, Eby G. Friedman
2023 J jnl
Temperature-frequency boundary of cryogenic dynamic logic.
Microelectron. J.
Nurzhan Zhuldassov, Eby G. Friedman
2023 J jnl
Thermal Optimization of Hybrid Cryogenic Computing Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Nurzhan Zhuldassov, Rassul Bairamkulov, Eby G. Friedman
2022 C conf
Converter Topologies for On-Package Voltage Stacking.
ISCAS
Nurzhan Zhuldassov, Kan Xu, Eby G. Friedman
2022 C conf
Double Magnetic Tunnel Junction-Based Nonvolatile Logic.
ISCAS
Abdelrahman G. Qoutb, Eby G. Friedman
2022 J jnl
Inductive noise coupling in multilayer superconductive ICs.
Microelectron. J.
Gleb Krylov, Eby G. Friedman
2022 J jnl
QuCTS - Single-Flux Quantum Clock Tree Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rassul Bairamkulov, Tahereh Jabbari, Eby G. Friedman
2022 J jnl
SPROUT - Smart Power Routing Tool for Board-Level Exploration and Prototyping.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rassul Bairamkulov, Abinash Roy, Mahalingam Nagarajan, Vaishnav Srinivas, Eby G. Friedman
2022 J jnl
Superconductive Logic Using 2ϕ - Josephson Junctions With Half Flux Quantum Pulses.
IEEE Trans. Circuits Syst. II Express Briefs
Issa Salameh, Eby G. Friedman, Shahar Kvatinsky
2022 J jnl
Surface Inductance of Superconductive Striplines.
IEEE Trans. Circuits Syst. II Express Briefs
Tahereh Jabbari, Eby G. Friedman
2021 — conf
Inductive Noise Coupling in Superconductive Passive Transmission Lines.
MWSCAS
Gleb Krylov, Eby G. Friedman
2021 C conf
MTJ-Based Dithering for Stochastic Analog-to-Digital Conversion.
ISCAS
Ana Mitrovic, Eby G. Friedman
2021 A* conf
SPROUT - Smart Power ROUting Tool for Board-Level Exploration and Prototyping.
DAC
Rassul Bairamkulov, Abinash Roy, Mali Nagarajan, Vaishnav Srinivas, Eby G. Friedman
2020 C conf
Bias Distribution in ERSFQ VLSI Circuits.
ISCAS
Gleb Krylov, Eby G. Friedman
2020 C conf
Challenges in High Current On-Chip Voltage Stacked Systems.
ISCAS
Kan Xu, Eby G. Friedman
2020 C conf
Cryogenic Dynamic Logic.
ISCAS
Nurzhan Zhuldassov, Eby G. Friedman
2020 J jnl
Design Methodology for Distributed Large-Scale ERSFQ Bias Networks.
IEEE Trans. Very Large Scale Integr. Syst.
Gleb Krylov, Eby G. Friedman
2020 J jnl
Distributed Pass Gates in Power Delivery Systems With Digital Low-Dropout Regulators.
IEEE Trans. Very Large Scale Integr. Syst.
Albert Ciprut, Eby G. Friedman
2020 C conf
Distributed Port Assignment for Extraction of Power Delivery Networks.
ISCAS
Kan Xu, Eby G. Friedman, Mikhail Popovich, Gregory Sizikov
2020 J jnl
Distributed Spintronic/CMOS Sensor Network for Thermal-Aware Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Abdelrahman G. Qoutb, Eby G. Friedman
2020 J jnl
Effective Resistance of Finite Two-Dimensional Grids Based on Infinity Mirror Technique.
IEEE Trans. Circuits Syst. I Regul. Pap.
Rassul Bairamkulov, Eby G. Friedman
2020 — conf
Global interconnects in VLSI complexity single flux quantum systems.
SLIP
Tahereh Jabbari, Eby G. Friedman
2020 C conf
Graph-Based Power Network Routing for Board-Level High Performance Systems.
ISCAS
Rassul Bairamkulov, Eby G. Friedman, Abinash Roy, Mali Nagarajan, Vaishnav Srinivas
2020 C conf
Multi-Bit CNT TSV for 3-D ICs.
ISCAS
Boris Vaisband, Ange Maurice, Chong Wei Tan, Beng Kang Tay, Eby G. Friedman
2020 J jnl
Power Delivery Exploration Methodology Based on Constrained Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rassul Bairamkulov, Kan Xu, Mikhail Popovich, Juan Ochoa, Vaishnav Srinivas, Eby G. Friedman
2020 C conf
Spintronic/CMOS-Based Thermal Sensors.
ISCAS
Abdelrahman G. Qoutb, Eby G. Friedman
2019 J jnl
Effective Resistance of Two-Dimensional Truncated Infinite Mesh Structures.
IEEE Trans. Circuits Syst. I Regul. Pap.
Rassul Bairamkulov, Eby G. Friedman
2019 C conf
PMTJ Temperature Sensor Utilizing VCMA.
ISCAS
Abdelrahman G. Qoutb, Eby G. Friedman
2019 J jnl
Stability of On-Chip Power Delivery Systems With Multiple Low-Dropout Regulators.
IEEE Trans. Very Large Scale Integr. Syst.
Albert Ciprut, Eby G. Friedman
2018 C conf
Behavioral Verilog-A Model of Superconductor-Ferromagnetic Transistor.
ISCAS
Gleb Krylov, Eby G. Friedman
2018 J jnl
Energy-Efficient Write Scheme for Nonvolatile Resistive Crossbar Arrays With Selectors.
IEEE Trans. Very Large Scale Integr. Syst.
Albert Ciprut, Eby G. Friedman
2018 J jnl
Exploratory design of on-chip power delivery for 14, 10, and 7 nm and beyond FinFET ICs.
Integr.
Kan Xu, Ravi Patel, Praveen Raghavan, Eby G. Friedman
2018 J jnl
Heterogeneous 3-D ICs as a platform for hybrid energy harvesting in IoT systems.
Future Gener. Comput. Syst.
Boris Vaisband, Eby G. Friedman
2018 C conf
Hybrid Write Bias Scheme for Non-Volatile Resistive Crossbar Arrays.
ISCAS
Albert Ciprut, Eby G. Friedman
2018 — conf
MTJ Magnetization Switching Mechanisms for IoT Applications.
ACM Great Lakes Symposium on VLSI
Abdelrahman G. Qoutb, Eby G. Friedman
2018 J jnl
Memristor-Based Circuit Design for Multilayer Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yang Zhang, Xiaoping Wang, Eby G. Friedman
2018 — conf
On the write energy of non-volatile resistive crossbar arrays with selectors.
ISQED
Albert Ciprut, Eby G. Friedman
2018 C conf
Versatile Framework for Power Delivery Exploration.
ISCAS
Rassul Bairamkulov, Kan Xu, Eby G. Friedman, Mikhail Popovich, Juan Ochoa, Vaishnav Srinivas
2017 J jnl
Hexagonal TSV Bundle Topology for 3-D ICs.
IEEE Trans. Circuits Syst. II Express Briefs
Boris Vaisband, Eby G. Friedman
2017 C conf
Hybrid energy harvesting in 3-D IC IoT devices.
ISCAS
Boris Vaisband, Eby G. Friedman
2017 J jnl
Interconnect Delay Model for Wide Supply Voltage Range Repeater Insertion in Sub-22 nm FinFET Technologies.
J. Low Power Electron.
Alexander E. Shapiro, Eby G. Friedman
2017 J jnl
Memristive Model for Synaptic Circuits.
IEEE Trans. Circuits Syst. II Express Briefs
Yang Zhang, Xiaoping Wang, Yi Li, Eby G. Friedman
2017 J jnl
Modeling Size Limitations of Resistive Crossbar Array With Cell Selectors.
IEEE Trans. Very Large Scale Integr. Syst.
Albert Ciprut, Eby G. Friedman
2017 — conf
On the stability of distributed on-chip low dropout regulators.
MWSCAS
Albert Ciprut, Eby G. Friedman
2017 C conf
Test point insertion for RSFQ circuits.
ISCAS
Gleb Krylov, Eby G. Friedman
2016 J jnl
Adaptive power gating of 32-bit Kogge Stone adder.
Integr.
Alexander E. Shapiro, Francois Atallah, Kyugseok Kim, Jihoon Jeong, Jeff Fischer, Eby G. Friedman
2016 J jnl
Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOS.
IEEE Trans. Very Large Scale Integr. Syst.
Yuxin Bai, Yanwei Song, Mahdi Nazm Bojnordi, Alexander E. Shapiro, Eby G. Friedman, Engin Ipek
2016 C conf
Design models of resistive crossbar arrays with selector devices.
ISCAS
Albert Ciprut, Eby G. Friedman
2016 — conf
Exploratory Power Noise Models of Standard Cell 14, 10, and 7 nm FinFET ICs.
ACM Great Lakes Symposium on VLSI
Ravi Patel, Kan Xu, Eby G. Friedman, Praveen Raghavan
2016 J jnl
Heterogeneous 3-D circuits: Integrating free-space optics with CMOS.
Microelectron. J.
Ioannis Savidis, Berkehan Ciftcioglu, Jie Xu, Jianyun Hu, Manish Jain, Rebecca Berman, Jing Xue, Peng Liu, Duncan Moore, Gary Wicks, Michael C. Huang, Hui Wu, Eby G. Friedman
2016 C conf
Layer ordering to minimize TSVs in heterogeneous 3-D ICs.
ISCAS
Boris Vaisband, Eby G. Friedman
2016 J jnl
Noise Coupling Models in Heterogeneous 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst.
Boris Vaisband, Eby G. Friedman
2016 J jnl
PNS-FCR: Flexible Charge Recycling Dynamic Circuit Technique for Low-Power Microprocessors.
IEEE Trans. Very Large Scale Integr. Syst.
Jinhui Wang, Na Gong, Eby G. Friedman
2016 J jnl
Power Efficient Level Shifter for 16 nm FinFET Near Threshold Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Alexander E. Shapiro, Eby G. Friedman
2016 C conf
Power noise in 14, 10, and 7 nm FinFET CMOS technologies.
ISCAS
Ravi Patel, Eby G. Friedman, Praveen Raghavan
2016 J jnl
Reducing Switching Latency and Energy in STT-MRAM Caches With Field-Assisted Writing.
IEEE Trans. Very Large Scale Integr. Syst.
Ravi Patel, Xiaochen Guo, Qing Guo, Engin Ipek, Eby G. Friedman
2015 C conf
3-D floorplanning algorithm to minimize thermal interactions.
ISCAS
Boris Vaisband, Eby G. Friedman
2015 C conf
Architecting a MOS current mode logic (MCML) processor for fast, low noise and energy-efficient computing in the near-threshold regime.
ICCD
Yuxin Bai, Yanwei Song, Mahdi Nazm Bojnordi, Alexander E. Shapiro, Engin Ipek, Eby G. Friedman
2015 J jnl
Energy efficient adaptive clustering of on-chip power delivery systems.
Integr.
Inna Vaisband, Eby G. Friedman
2015 J jnl
Energy-Efficient Nonvolatile Flip-Flop With Subnanosecond Data Backup Time for Fine-Grain Power Gating.
IEEE Trans. Circuits Syst. II Express Briefs
Mohammad Kazemi, Engin Ipek, Eby G. Friedman
2015 J jnl
Experimental Analysis of Thermal Coupling in 3-D Integrated Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Ioannis Savidis, Boris Vaisband, Eby G. Friedman
2015 C conf
Inductive coupling effects in large TSV arrays.
ISCAS
Kan Xu, Eby G. Friedman
2015 J jnl
Multistate Register Based on Resistive RAM.
IEEE Trans. Very Large Scale Integr. Syst.
Ravi Patel, Shahar Kvatinsky, Eby G. Friedman, Avinoam Kolodny
2015 J jnl
Resistive Ternary Content Addressable Memory Systems for Data-Intensive Computing.
IEEE Micro
Qing Guo, Xiaochen Guo, Yuxin Bai, Ravi Patel, Engin Ipek, Eby G. Friedman
2015 J jnl
Scaling trends of power noise in 3-D ICs.
Integr.
Kan Xu, Eby G. Friedman
2015 J jnl
VTEAM: A General Model for Voltage-Controlled Memristors.
IEEE Trans. Circuits Syst. II Express Briefs
Shahar Kvatinsky, Misbah Ramadan, Eby G. Friedman, Avinoam Kolodny
2014 J jnl
2T-1R STT-MRAM memory cells for enhanced on/off current ratio.
Microelectron. J.
Ravi Patel, Engin Ipek, Eby G. Friedman
2014 C conf
Computationally efficient clustering of power supplies in heterogeneous real time systems.
ISCAS
Inna Vaisband, Eby G. Friedman
2014 J jnl
Digitally Controlled Pulse Width Modulator for On-Chip Power Management.
IEEE Trans. Very Large Scale Integr. Syst.
Inna Vaisband, Mahmood J. Azhar, Eby G. Friedman, Selçuk Köse
2014 — conf
Dynamic power management with power network-on-chip.
NEWCAS
Inna Vaisband, Eby G. Friedman
2014 C conf
Field driven STT-MRAM cell for reduced switching latency and energy.
ISCAS
Ravi Patel, Engin Ipek, Eby G. Friedman
2014 J jnl
Logic operations in memory using a memristive Akers array.
Microelectron. J.
Yifat Levy, Jehoshua Bruck, Yuval Cassuto, Eby G. Friedman, Avinoam Kolodny, Eitan Yaakobi, Shahar Kvatinsky
2014 J jnl
MAGIC - Memristor-Aided Logic.
IEEE Trans. Circuits Syst. II Express Briefs
Shahar Kvatinsky, Dmitry Belousov, Slavik Liman, Guy Satat, Nimrod Wald, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser
2014 J jnl
Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies.
IEEE Trans. Very Large Scale Integr. Syst.
Shahar Kvatinsky, Guy Satat, Nimrod Wald, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser
2014 J jnl
Memristor-Based Multithreading.
IEEE Comput. Archit. Lett.
Shahar Kvatinsky, Yuval H. Nacson, Yoav Etsion, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser
2014 — conf
Power network-on-chip for scalable power delivery.
SLIP
Inna Vaisband, Eby G. Friedman
2014 — conf
Sub-crosspoint RRAM decoding for improved area efficiency.
NANOARCH
Ravi Patel, Eby G. Friedman
2014 C conf
Thermal conduction path analysis in 3-D ICs.
ISCAS
Boris Vaisband, Ioannis Savidis, Eby G. Friedman
2013 A* conf
AC-DIMM: associative computing with STT-MRAM.
ISCA
Qing Guo, Xiaochen Guo, Ravi Patel, Engin Ipek, Eby G. Friedman
2013 J jnl
Active Filter-Based Hybrid On-Chip DC-DC Converter for Point-of-Load Voltage Regulation.
IEEE Trans. Very Large Scale Integr. Syst.
Selçuk Köse, Simon Tam, Sally Pinzon, Bruce McDermott, Eby G. Friedman
2013 C conf
Current profile of a microcontroller to determine electromagnetic emissions.
ISCAS
Selçuk Köse, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin
2013 J jnl
Data bus swizzling in TSV-based three-dimensional integrated circuits.
Microelectron. J.
Shen Ge, Eby G. Friedman
2013 C conf
Digitally controlled wide range pulse width modulator for on-chip power supplies.
ISCAS
Selçuk Köse, Inna Vaisband, Eby G. Friedman
2013 J jnl
Power Network Optimization Based on Link Breaking Methodology.
IEEE Trans. Very Large Scale Integr. Syst.
Renatas Jakushokas, Eby G. Friedman
2013 J jnl
Power Noise in TSV-Based 3-D Integrated Circuits.
IEEE J. Solid State Circuits
Ioannis Savidis, Selçuk Köse, Eby G. Friedman
2013 J jnl
TEAM: ThrEshold Adaptive Memristor Model.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shahar Kvatinsky, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser
2013 J jnl
Timing-driven variation-aware synthesis of hybrid mesh/tree clock distribution networks.
Integr.
Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman
2012 — conf
An area efficient on-chip hybrid voltage regulator.
ISQED
Selçuk Köse, Eby G. Friedman, Simon Tarn, Sally Pinzon, Bruce McDermott
2012 C conf
Arithmetic encoding for memristive multi-bit storage.
VLSI-SoC
Ravi Patel, Eby G. Friedman
2012 J jnl
Distributed On-Chip Power Delivery.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Selçuk Köse, Eby G. Friedman
2012 — conf
Distributed power delivery for energy efficient and low power systems.
ACSCC
Selçuk Köse, Eby G. Friedman
2012 J jnl
Efficient algorithms for fast IR drop analysis exploiting locality.
Integr.
Selçuk Köse, Eby G. Friedman
2012 C conf
Energy metrics for power efficient crosslink and mesh topologies.
ISCAS
Inna Vaisband, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny
2012 — conf
Link breaking methodology: mitigating noise within power networks.
ACM Great Lakes Symposium on VLSI
Renatas Jakushokas, Eby G. Friedman
2012 J jnl
Multi-aggressor capacitive and inductive coupling noise modeling and mitigation.
Microelectron. J.
Victoria Vishnyakov, Eby G. Friedman, Avinoam Kolodny
2012 — conf
STT-MRAM memory cells with enhanced on/off ratio.
SoCC
Ravi Patel, Engin Ipek, Eby G. Friedman
2012 J jnl
Utilizing interdependent timing constraints to enhance robustness in synchronous circuits.
Microelectron. J.
Emre Salman, Eby G. Friedman
2011 J jnl
A Distributed Filter Within a Switching Converter for Application to 3-D Integrated Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Jonathan Rosenfeld, Eby G. Friedman
2011 J jnl
Clock Distribution Networks in 3-D Integrated Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Vasilis F. Pavlidis, Ioannis Savidis, Eby G. Friedman
2011 C conf
Clock distribution models of 3-D integrated systems.
ISCAS
Ioannis Savidis, Vasilis F. Pavlidis, Eby G. Friedman
2011 — conf
Distributed power network co-design with on-chip power supplies and decoupling capacitors.
SLIP
Selçuk Köse, Eby G. Friedman
2011 J jnl
Effective Resistance of a Two Layer Mesh.
IEEE Trans. Circuits Syst. II Express Briefs
Selçuk Köse, Eby G. Friedman
2011 A* conf
Fast algorithms for
DAC
Selçuk Köse, Eby G. Friedman
2011 J jnl
Linear and Switch-Mode Conversion in 3-D Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Jonathan Rosenfeld, Eby G. Friedman
2011 C conf
Memristor-based IMPLY logic design procedure.
ICCD
Shahar Kvatinsky, Avinoam Kolodny, Uri C. Weiser, Eby G. Friedman
2011 J jnl
Multi-Layer Interdigitated Power Distribution Networks.
IEEE Trans. Very Large Scale Integr. Syst.
Renatas Jakushokas, Eby G. Friedman
2011 — ch.
Physical Analysis of NoC Topologies for 3-D Integrated Systems.
3D Integration for NoC-based SoC Architectures
Vasilis F. Pavlidis, Eby G. Friedman
2011 J jnl
Shielding Methodologies in the Presence of Power/Ground Noise.
IEEE Trans. Very Large Scale Integr. Syst.
Selçuk Köse, Emre Salman, Eby G. Friedman
2011 J jnl
Thermal analysis of oxide-confined VCSEL arrays.
Microelectron. J.
Jinhui Wang, Ioannis Savidis, Eby G. Friedman
2010 C conf
An area efficient fully monolithic hybrid voltage regulator.
ISCAS
Selçuk Köse, Eby G. Friedman
2010 A* conf
An intra-chip free-space optical interconnect.
ISCA
Jing Xue, Alok Garg, Berkehan Ciftcioglu, Jianyun Hu, Shang Wang, Ioannis Savidis, Manish Jain, Rebecca Berman, Peng Liu, Michael C. Huang, Hui Wu, Eby G. Friedman, Gary Wicks, Duncan Moore
2010 C conf
Compact substrate models for efficient noise coupling and signal isolation analysis.
ISCAS
Renatas Jakushokas, Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin, Cynthia L. Recker
2010 J jnl
Corrections to "Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect" [May 10 689-696].
IEEE Trans. Very Large Scale Integr. Syst.
Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny
2010 — conf
Efficiency optimization of integrated DC-DC buck converters.
ICECS
Gregory Sizikov, Avinoam Kolodny, Eby G. Friedman, Michael Zelikson
2010 C conf
Fast algorithms for power grid analysis based on effective resistance.
ISCAS
Selçuk Köse, Eby G. Friedman
2010 C conf
Globally integrated power and clock distribution network.
ISCAS
Renatas Jakushokas, Eby G. Friedman
2010 — conf
Line width optimization for interdigitated power/ground networks.
ACM Great Lakes Symposium on VLSI
Renatas Jakushokas, Eby G. Friedman
2010 C conf
Methodology for multi-layer interdigitated power and ground network design.
ISCAS
Renatas Jakushokas, Eby G. Friedman
2010 — conf
Methodology to achieve higher tolerance to delay variations in synchronous circuits.
ACM Great Lakes Symposium on VLSI
Emre Salman, Eby G. Friedman
2010 — conf
On-chip point-of-load voltage regulator for distributed power supplies.
ACM Great Lakes Symposium on VLSI
Selçuk Köse, Eby G. Friedman
2010 J jnl
Resource Based Optimization for Simultaneous Shield and Repeater Insertion.
IEEE Trans. Very Large Scale Integr. Syst.
Renatas Jakushokas, Eby G. Friedman
2010 — conf
Simultaneous co-design of distributed on-chip power supplies and decoupling capacitors.
SoCC
Selçuk Köse, Eby G. Friedman
2010 — conf
Timing-driven variation-aware nonuniform clock mesh synthesis.
ACM Great Lakes Symposium on VLSI
Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman
2010 J jnl
Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect.
IEEE Trans. Very Large Scale Integr. Syst.
Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny
2009 — conf
Contact merging algorithm for efficient substrate noise analysis in large scale circuits.
ACM Great Lakes Symposium on VLSI
Emre Salman, Renatas Jakushokas, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin
2009 — conf
Design challenges in high performance three-dimensional circuits.
ACM Great Lakes Symposium on VLSI
Eby G. Friedman
2009 J jnl
Identification of Dominant Noise Source and Parameter Sensitivity for Substrate Coupling.
IEEE Trans. Very Large Scale Integr. Syst.
Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin
2009 J jnl
Inductance Model of Interdigitated Power and Ground Distribution Networks.
IEEE Trans. Circuits Syst. II Express Briefs
Renatas Jakushokas, Eby G. Friedman
2009 J jnl
Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits.
Proc. IEEE
Vasilis F. Pavlidis, Eby G. Friedman
2009 J jnl
Methodology for Efficient Substrate Noise Analysis in Large-Scale Mixed-Signal Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Emre Salman, Renatas Jakushokas, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin
2009 C conf
Minimizing Noise Via Shield and Repeater Insertion.
ISCAS
Renatas Jakushokas, Eby G. Friedman
2009 — conf
On-chip DC-DC converters for three-dimensional ICs.
ISQED
Jonathan Rosenfeld, Eby G. Friedman
2009 — conf
Power efficient tree-based crosslinks for skew reduction.
ACM Great Lakes Symposium on VLSI
Inna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman
2009 J jnl
Quasi-Resonant Interconnects: A Low Power, Low Latency Design Methodology.
IEEE Trans. Very Large Scale Integr. Syst.
Jonathan Rosenfeld, Eby G. Friedman
2009 C conf
Shielding Methodologies in the Presence of Power/Ground Noise.
ISCAS
Selçuk Köse, Emre Salman, Eby G. Friedman
2009 — conf
Simultaneous shield and repeater insertion.
ACM Great Lakes Symposium on VLSI
Renatas Jakushokas, Eby G. Friedman
2009 J jnl
Transient Response of a Distributed RLC Interconnect Based on Direct Pole Extraction.
J. Circuits Syst. Comput.
Guoqing Chen, Eby G. Friedman
2009 J jnl
Worst Case Power/Ground Noise Estimation Using an Equivalent Transition Time for Resonance.
IEEE Trans. Circuits Syst. I Regul. Pap.
Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin
2008 — conf
A higher-order mismatch-shaping method for multi-bit Sigma-Delta Modulators.
SoCC
Alexander Lavzin, Mücahit Kozak, Eby G. Friedman
2008 — conf
Clock distribution networks for 3-D ictegrated Circuits.
CICC
Vasilis F. Pavlidis, Ioannis Savidis, Eby G. Friedman
2008 — conf
Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates.
ISQED
Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin
2008 J jnl
Effective Capacitance of Inductive Interconnects for Short-Circuit Power Analysis.
IEEE Trans. Circuits Syst. II Express Briefs
Guoqing Chen, Eby G. Friedman
2008 J jnl
Effective Radii of On-Chip Decoupling Capacitors.
IEEE Trans. Very Large Scale Integr. Syst.
Mikhail Popovich, Michael Sotman, Avinoam Kolodny, Eby G. Friedman
2008 J jnl
Efficient Distributed On-Chip Decoupling Capacitors for Nanoscale ICs.
IEEE Trans. Very Large Scale Integr. Syst.
Mikhail Popovich, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin
2008 C conf
Electrical modeling and characterization of 3-D vias.
ISCAS
Ioannis Savidis, Eby G. Friedman
2008 C conf
Equivalent rise time for resonance in power/ground noise estimation.
ISCAS
Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin
2008 C conf
Input port reduction for efficient substrate extraction in large scale IC's.
ISCAS
Emre Salman, Renatas Jakushokas, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin
2008 — conf
Nanoscale on-chip decoupling capacitors.
SoCC
Mikhail Popovich, Eby G. Friedman
2008 J jnl
On-Chip Power Distribution Grids With Multiple Supply Voltages for High-Performance Integrated Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny
2008 — conf
Physical Design Issues in 3-D Integrated Technologies.
VLSI-SoC (Selected Papers)
Vasilis F. Pavlidis, Eby G. Friedman
2008 — conf
Pseudo-random clocking to enhance signal integrity.
SoCC
Selçuk Köse, Emre Salman, Zeljko Ignjatovic, Eby G. Friedman
2008 — conf
Timing optimization in logic with interconnect.
SLIP
Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny
2008 J jnl
Timing-driven via placement heuristics for three-dimensional ICs.
Integr.
Vasilis F. Pavlidis, Eby G. Friedman
2008 C conf
Transient simulation of on-chip transmission lines via exact pole extraction.
ISCAS
Guoqing Chen, Eby G. Friedman
2007 J jnl
3-D Topologies for Networks-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst.
Vasilis F. Pavlidis, Eby G. Friedman
2007 J jnl
Design Methodology for Global Resonant H-Tree Clock Distribution Networks.
IEEE Trans. Very Large Scale Integr. Syst.
Jonathan Rosenfeld, Eby G. Friedman
2007 A conf
Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs.
ICCAD
Mikhail Popovich, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin
2007 J jnl
Exploiting Setup-Hold-Time Interdependence in Static Timing Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Emre Salman, Ali Dasdan, Feroze Taraporevala, Kayhan Küçükçakar, Eby G. Friedman
2007 — conf
On-chip optical interconnect for reduced delay uncertainty.
Nano-Net
Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, David H. Albonesi, Philippe M. Fauchet, Eby G. Friedman
2007 J jnl
Predictions of CMOS compatible on-chip optical interconnect.
Integr.
Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, David H. Albonesi, Philippe M. Fauchet, Eby G. Friedman
2007 C conf
Quasi-Resonant Interconnects: A Low Power Design Methodology.
ISCAS
Jonathan Rosenfeld, Eby G. Friedman
2007 C conf
Substrate Noise Reduction Based On Noise Aware Cell Design.
ISCAS
Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin
2007 J jnl
Wire shaping of RLC interconnects.
Integr.
Magdy A. El-Moursy, Eby G. Friedman
2006 — conf
3-D Topologies for Networks-on-Chip.
SoCC
Vasilis F. Pavlidis, Eby G. Friedman
2006 J jnl
Crosstalk modeling for coupled RLC interconnects with application to shield insertion.
IEEE Trans. Very Large Scale Integr. Syst.
Junmou Zhang, Eby G. Friedman
2006 J jnl
Decoupling capacitors for multi-voltage power distribution systems.
IEEE Trans. Very Large Scale Integr. Syst.
Mikhail Popovich, Eby G. Friedman
2006 C conf
Design methodology for global resonant H-tree clock distribution networks.
ISCAS
Jonathan Rosenfeld, Eby G. Friedman
2006 C conf
Effective capacitance of RLC loads for estimating short-circuit power.
ISCAS
Guoqing Chen, Eby G. Friedman
2006 J jnl
Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints.
IEEE Trans. Very Large Scale Integr. Syst.
Guoqing Chen, Eby G. Friedman
2006 — conf
Maximum effective distance of on-chip decoupling capacitors in power distribution grids.
ACM Great Lakes Symposium on VLSI
Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny, Radu M. Secareanu
2006 J jnl
On-chip test circuit for measuring substrate and line-to-line coupling noise.
IEEE J. Solid State Circuits
Weize Xu, Eby G. Friedman
2006 C conf
On-die decoupling capacitance: frequency domain analysis of activity radius.
ISCAS
Michael Sotman, Avinoam Kolodny, Mikhail Popovich, Eby G. Friedman
2006 C conf
Optimum wire tapering for minimum power dissipation in RLC interconnects.
ISCAS
Magdy A. El-Moursy, Eby G. Friedman
2006 — conf
Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times.
ISQED
Emre Salman, Eby G. Friedman, Ali Dasdan, Feroze Taraporevala, Kayhan Küçükçakar
2006 — conf
Sensitivity evaluation of global resonant H-tree clock distribution networks.
ACM Great Lakes Symposium on VLSI
Jonathan Rosenfeld, Eby G. Friedman
2006 J jnl
Sizing CMOS inverters with Miller Effect and Threshold voltage Variations.
J. Circuits Syst. Comput.
Boris D. Andreev, Edward L. Titlebaum, Eby G. Friedman
2006 — conf
Substrate and Ground Noise Interactions in Mixed-Signal Circuits.
SoCC
Emre Salman, Eby G. Friedman, Radu M. Secareanu
2006 C conf
Via placement for minimum interconnect delay in three-dimensional (3D) circuits.
ISCAS
Vasilis F. Pavlidis, Eby G. Friedman
2005 — conf
A Fourier series-based RLC interconnect model for periodic signals.
ISCAS (4)
Guoqing Chen, Eby G. Friedman
2005 J jnl
An RLC interconnect model based on fourier analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Guoqing Chen, Eby G. Friedman
2005 — conf
Cascode buffer for monolithic voltage conversion operating at high input supply voltages.
ISCAS (1)
Volkan Kursun, Gerhard Schrom, Vivek De, Eby G. Friedman, Siva G. Narendra
2005 — conf
Electrical and optical on-chip interconnects in scaled microprocessors.
ISCAS (3)
Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi
2005 J jnl
Exponentially tapered H-tree clock distribution networks.
IEEE Trans. Very Large Scale Integr. Syst.
Magdy A. El-Moursy, Eby G. Friedman
2005 — conf
Interconnect delay minimization through interlayer via placement in 3-D ICs.
ACM Great Lakes Symposium on VLSI
Vasilis F. Pavlidis, Eby G. Friedman
2005 — conf
Low power repeaters driving RLC interconnects with delay and bandwidth constraints.
ISCAS (1)
Guoqing Chen, Eby G. Friedman
2005 — conf
Managing substrate and interconnect noise from high performance repeater insertion in a mixed-signal environment.
ISCAS (1)
Radu M. Secareanu, Suman K. Banerjee, Olin L. Hartin, Virgilio Fernandez, Eby G. Friedman
2005 J jnl
Monolithic voltage conversion in low-voltage CMOS technologies.
Microelectron. J.
Volkan Kursun, Vivek De, Eby G. Friedman, Siva G. Narendra
2005 — conf
Noise Aware Decoupling Capacitors for Multi-Voltage Power Distribution Systems.
ISQED
Mikhail Popovich, Eby G. Friedman
2005 — conf
Noise coupling in multi-voltage power distribution systems with decoupling capacitors.
ISCAS (1)
Mikhail Popovich, Eby G. Friedman
2005 — conf
On-Chip Power Noise Reduction Techniques in High Performance SoC-Based Integrated Circuits.
SoCC
Mikhail Popovich, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin
2005 — conf
On-chip power distribution grids with multiple supply voltages for high performance integrated circuits.
ACM Great Lakes Symposium on VLSI
Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny
2005 — conf
Predictions of CMOS compatible on-chip optical interconnect.
SLIP
Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi
2005 J jnl
Shielding effect of on-chip interconnect inductance.
IEEE Trans. Very Large Scale Integr. Syst.
Magdy A. El-Moursy, Eby G. Friedman
2004 — conf
A 250 MHz delta-sigma modulator for low cost ultrasound/sonar beamforming applications.
ICECS
Boaz Shem-Tov, Mücahit Kozak, Eby G. Friedman
2004 — conf
A bulk-driven CMOS OTA with 68 dB DC gain.
ICECS
Jonathan Rosenfeld, Mücahit Kozak, Eby G. Friedman
2004 — conf
A high-speed CMOS op-amp design technique using negative Miller capacitance.
ICECS
Boaz Shem-Tov, Mücahit Kozak, Eby G. Friedman
2004 — conf
A low power thyristor-based CMOS programmable delay element.
ISCAS (1)
Junmou Zhang, Simon R. Cooper, Andrew R. LaPietra, Michael W. Mattern, Robert M. Guidash, Eby G. Friedman
2004 — conf
Buffer Sizing for Crosstalk Induced Delay Uncertainty.
PATMOS
Dimitrios Velenis, Eby G. Friedman
2004 — conf
Buffer sizing for delay uncertainty induced by process variations.
ICECS
Dimitrios Velenis, Ramyashree Sundaresha, Eby G. Friedman
2004 — conf
Challenges in ultra deep submicrometer high performance VLSI circuits.
ICECS
Eby G. Friedman
2004 — conf
Clock tree layout design for reduced delay uncertainty.
SoCC
Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman
2004 J jnl
Complex +/-1 Multiplier Based on Signed-Binary Transformations.
J. VLSI Signal Process.
Boris D. Andreev, Edward L. Titlebaum, Eby G. Friedman
2004 — conf
Decoupling capacitors for power distribution systems with multiple power supply voltages.
SoCC
Mikhail Popovich, Eby G. Friedman
2004 — conf
Decoupling technique and crosstalk analysis for coupled RLC interconnects.
ISCAS (2)
Junmou Zhang, Eby G. Friedman
2004 — conf
Design and simulation of Fractional-N PLL frequency synthesizers.
ISCAS (4)
Mücahit Kozak, Eby G. Friedman
2004 — conf
Effect of shield insertion on reducing crosstalk noise between coupled interconnects.
ISCAS (2)
Junmou Zhang, Eby G. Friedman
2004 — conf
Energy efficient dual threshold voltage dynamic circuits employing sleep switches to minimize subthreshold leakage.
ISCAS (2)
Volkan Kursun, Eby G. Friedman
2004 — conf
Exponentially tapered H-tree clock distribution networks.
ISCAS (2)
Magdy A. El-Moursy, Eby G. Friedman
2004 — conf
Forward body biased keeper for enhanced noise immunity in domino logic circuits.
ISCAS (2)
Volkan Kursun, Eby G. Friedman
2004 — conf
High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS Process.
ISQED
Volkan Kursun, Siva G. Narendra, Vivek De, Eby G. Friedman
2004 — conf
Impedance characteristics of decoupling capacitors in multi-power distribution systems.
ICECS
Mikhail Popovich, Eby G. Friedman
2004 J jnl
Impedance characteristics of power distribution grids in nanoscale integrated circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Andrey V. Mezhiba, Eby G. Friedman
2004 — conf
Low power flexible Rake receivers for WCDMA.
ISCAS (4)
Boris D. Andreev, Edward L. Titlebaum, Eby G. Friedman
2004 — conf
Low power repeaters driving RC interconnects with delay and bandwidth constraints.
SoCC
Guoqing Chen, Eby G. Friedman
2004 J jnl
Low-voltage-swing monolithic dc-dc conversion.
IEEE Trans. Circuits Syst. II Express Briefs
Volkan Kursun, Siva G. Narendra, Vivek K. De, Eby G. Friedman
2004 — conf
Mutual inductance modeling for multiple RLC interconnects with application to shield insertion.
SoCC
Junmou Zhang, Eby G. Friedman
2004 — conf
Node Voltage Dependent Subthreshold Leakage Current Characteristics of Dynamic Circuits.
ISQED
Volkan Kursun, Eby G. Friedman
2004 J jnl
Optimum wire sizing of
Integr.
Magdy A. El-Moursy, Eby G. Friedman
2004 J jnl
Power characteristics of inductive interconnect.
IEEE Trans. Very Large Scale Integr. Syst.
Magdy A. El-Moursy, Eby G. Friedman
2004 J jnl
Scaling trends of on-chip power distribution noise.
IEEE Trans. Very Large Scale Integr. Syst.
Andrey V. Mezhiba, Eby G. Friedman
2004 J jnl
Sleep switch dual threshold Voltage domino logic with reduced standby leakage current.
IEEE Trans. Very Large Scale Integr. Syst.
Volkan Kursun, Eby G. Friedman
2004 J jnl
Substrate coupling in digital circuits in mixed-signal smart-power systems.
IEEE Trans. Very Large Scale Integr. Syst.
Radu M. Secareanu, Scott Warner, Scott Seabridge, Cathie Burke, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Ivan S. Kourtev, Eby G. Friedman
2003 J jnl
Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor.
IEEE Trans. Very Large Scale Integr. Syst.
Volkan Kursun, Siva G. Narendra, Vivek De, Eby G. Friedman
2003 J jnl
Domino logic with variable threshold voltage keeper.
IEEE Trans. Very Large Scale Integr. Syst.
Volkan Kursun, Eby G. Friedman
2003 J jnl
Dynamically Tuning Processor Resources with Adaptive Processing.
Computer
David H. Albonesi, Rajeev Balasubramonian, Steve Dropsho, Sandhya Dwarkadas, Eby G. Friedman, Michael C. Huang, Volkan Kursun, Grigorios Magklis, Michael L. Scott, Greg Semeraro, Pradip Bose, Alper Buyuktosunoglu, Peter W. Cook, Stanley Schuster
2003 — conf
Electrical characteristics of multi-layer power distribution grids.
ISCAS (5)
Andrey V. Mezhiba, Eby G. Friedman
2003 — conf
Inductive interconnect width optimization for low power.
ISCAS (5)
Magdy A. El-Moursy, Eby G. Friedman
2003 — conf
Monolithic DC-DC Converter Analysis And Mosfet Gate Voltage Optimization.
ISQED
Volkan Kursun, Siva G. Narendra, Vivek De, Eby G. Friedman
2003 J jnl
On the Extraction of On-Chip Inductance.
J. Circuits Syst. Comput.
Yehea I. Ismail, Eby G. Friedman
2003 — conf
Optimum wire sizing of RLC interconnect with repeaters.
ACM Great Lakes Symposium on VLSI
Magdy A. El-Moursy, Eby G. Friedman
2003 — conf
Orthogonal code generator for 3G wireless transceivers.
ACM Great Lakes Symposium on VLSI
Boris D. Andreev, Edward L. Titlebaum, Eby G. Friedman
2003 — conf
Power characteristics of inductive interconnect.
ICECS
Magdy A. El-Moursy, Eby G. Friedman
2003 A conf
Reduced Delay Uncertainty in High Performance Clock Distribution Networks.
DATE
Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman
2003 — conf
Shielding effect of on-chip interconnect inductance.
ACM Great Lakes Symposium on VLSI
Magdy A. El-Moursy, Eby G. Friedman
2003 — conf
Transformations of Signed-Binary Number Representations for Efficient VLSI Arithmetic.
IWSOC
Boris D. Andreev, Edward L. Titlebaum, Eby G. Friedman
2002 — conf
A substrate noise circuit for accurately testing mixed-signal ICs.
ISCAS (1)
Weize Xu, Eby G. Friedman
2002 J jnl
DTT: direct truncation of the transfer function - an alternative tomoment matching for tree structured interconnect.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yehea I. Ismail, Eby G. Friedman
2002 J jnl
Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling.
J. Circuits Syst. Comput.
Dimitrios Velenis, Kevin T. Tang, Ivan S. Kourtev, Victor Adler, Franklin Baez, Eby G. Friedman
2002 — conf
Efficient implementation of a complex ±1 multiplier.
ACM Great Lakes Symposium on VLSI
Boris D. Andreev, Eby G. Friedman, Edward L. Titlebaum
2002 J jnl
Inductance Effects in RLC Trees.
J. Circuits Syst. Comput.
Yehea I. Ismail, Eby G. Friedman, José Luis Neves
2002 — conf
Inductance/area/resistance tradeoffs in high performance power distribution grids.
ISCAS (1)
Andrey V. Mezhiba, Eby G. Friedman
2002 — conf
Inductive Characteristics of Power Distribution Grids in High Speed Integrated Circuits.
ISQED
Andrey V. Mezhiba, Eby G. Friedman
2002 J jnl
Inductive properties of high-performance power distribution grids.
IEEE Trans. Very Large Scale Integr. Syst.
Andrey V. Mezhiba, Eby G. Friedman
2002 — conf
Large scale clock skew scheduling techniques for improved reliability of digital synchronous VLSI circuits.
ISCAS (1)
Roy Mader, Eby G. Friedman, Ami Litman, Ivan S. Kourtev
2002 — conf
Low swing dual threshold voltage domino logic.
ACM Great Lakes Symposium on VLSI
Volkan Kursun, Eby G. Friedman
2002 A* conf
Managing static leakage energy in microprocessor functional units.
MICRO
Steve Dropsho, Volkan Kursun, David H. Albonesi, Sandhya Dwarkadas, Eby G. Friedman
2002 — conf
Properties of on-chip inductive current loops.
ACM Great Lakes Symposium on VLSI
Andrey V. Mezhiba, Eby G. Friedman
2002 J jnl
Retiming and clock scheduling for digital circuit optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
2002 — conf
Scaling trends of on-chip Power distribution noise.
SLIP
Andrey V. Mezhiba, Eby G. Friedman
2002 J jnl
Simultaneous switching noise in on-chip CMOS power distribution networks.
IEEE Trans. Very Large Scale Integr. Syst.
Kevin T. Tang, Eby G. Friedman
2001 — conf
A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty.
ISCAS (4)
Dimitrios Velenis, Eby G. Friedman, Marios C. Papaefthymiou
2001 — conf
A comparative study of the behavior of NMOS and CMOS digital circuits under substrate noise.
ICECS
Radu M. Secareanu, Scott Warner, Scott Seabridge, Cathie Burke, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Eby G. Friedman
2001 J jnl
Clock distribution networks in synchronous digital integrated circuits.
Proc. IEEE
Eby G. Friedman
2001 — conf
Demonstration of speed enhancements on an industrial circuit through application of non-zero clock skew scheduling.
ICECS
Dimitrios Velenis, Kevin T. Tang, Ivan S. Kourtev, Victor Adler, Franklin Baez, Eby G. Friedman
2001 — conf
Estimation of transient voltage fluctuations in the CMOS-based power distribution networks.
ISCAS (5)
Kevin T. Tang, Eby G. Friedman
2001 J jnl
Exploiting the on-chip inductance in high-speed clock distribution networks.
IEEE Trans. Very Large Scale Integr. Syst.
Yehea I. Ismail, Eby G. Friedman, José Luis Neves
2000 J jnl
Delay and noise estimation of CMOS logic gates driving coupled resistive-capacitive interconnections.
Integr.
Kevin T. Tang, Eby G. Friedman
2000 C conf
Delay and power expressions characterizing a CMOS inverter driving an RLC load.
ISCAS
Kevin T. Tang, Eby G. Friedman
2000 J jnl
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Yehea I. Ismail, Eby G. Friedman
2000 J jnl
Equivalent Elmore delay for RLC trees.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yehea I. Ismail, Eby G. Friedman, José Luis Neves
2000 — conf
Noise estimation due to signal activity for capacitively coupled CMOS logic gates.
ACM Great Lakes Symposium on VLSI
Kevin T. Tang, Eby G. Friedman
2000 C conf
Physical design to improve the noise immunity of digital circuits in a mixed-signal smart-power system.
ISCAS
Radu M. Secareanu, Scott Warner, Scott Seabridge, Cathie Burke, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Eby G. Friedman
2000 C conf
Sensitivity of interconnect delay to on-chip inductance.
ISCAS
Yehea I. Ismail, Eby G. Friedman
2000 C conf
Transient analysis of a CMOS inverter driving resistive interconnect.
ISCAS
Kevin T. Tang, Eby G. Friedman
2000 — conf
Transparent repeaters.
ACM Great Lakes Symposium on VLSI
Radu M. Secareanu, Eby G. Friedman
1999 — conf
A high precision CMOS current mirror/divider.
ISCAS (2)
Radu M. Secareanu, Eby G. Friedman
1999 — conf
A universal CMOS voltage interface circuit.
ISCAS (1)
Radu M. Secareanu, Eby G. Friedman, Juan Becerra, Scott Warner
1999 A conf
Clock skew scheduling for improved reliability via quadratic programming.
ICCAD
Ivan S. Kourtev, Eby G. Friedman
1999 A* conf
Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits.
DAC
Yehea I. Ismail, Eby G. Friedman
1999 A* conf
Equivalent Elmore Delay for
DAC
Yehea I. Ismail, Eby G. Friedman, José Luis Neves
1999 — conf
Exploiting hysteresis in a CMOS buffer.
ICECS
Radu M. Secareanu, Victor Adler, Eby G. Friedman
1999 J jnl
Figures of merit to characterize the importance of on-chip inductance.
IEEE Trans. Very Large Scale Integr. Syst.
Yehea I. Ismail, Eby G. Friedman, José Luis Neves
1999 — conf
Inductance Effects in RLC Trees.
Great Lakes Symposium on VLSI
Yehea I. Ismail, Eby G. Friedman, José Luis Neves
1999 — conf
Interconnect coupling noise in CMOS VLSI circuits.
ISPD
Kevin T. Tang, Eby G. Friedman
1999 A* conf
Maximizing Performance by Retiming and Clock Skew Scheduling.
DAC
Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
1999 A conf
Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits.
DATE
Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
1999 — conf
Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems.
Great Lakes Symposium on VLSI
Radu M. Secareanu, Ivan S. Kourtev, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Eby G. Friedman
1999 — conf
Peak crosstalk noise estimation in CMOS VLSI circuits.
ICECS
Kevin T. Tang, Eby G. Friedman
1999 — conf
Peak noise prediction in loosely coupled interconnect [VLSI circuits].
ISCAS (1)
Kevin T. Tang, Eby G. Friedman
1999 — conf
Repeater insertion in RLC lines for minimum propagation delay.
ISCAS (6)
Yehea I. Ismail, Eby G. Friedman
1999 A conf
Repeater insertion in tree structured inductive interconnect.
ICCAD
Yehea I. Ismail, Eby G. Friedman, José Luis Neves
1999 — conf
Signal waveform characterization in RLC trees.
ISCAS (6)
Yehea I. Ismail, Eby G. Friedman, José Luis Neves
1999 — ch.
System Timing.
The VLSI Handbook
Ivan S. Kourtev, Eby G. Friedman
1998 — conf
A repeater timing model and insertion algorithm to reduce delay in RC tree structures.
ICECS
Victor Adler, Eby G. Friedman
1998 J jnl
Automated Synthesis of Skew-Based Clock Distribution Networks.
VLSI Design
José Luis Neves, Eby G. Friedman
1998 — conf
Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines.
Great Lakes Symposium on VLSI
Yehea I. Ismail, Eby G. Friedman, José Luis Neves
1998 A* conf
Figures of Merit to Characterize the Importance of On-Chip Inductance.
DAC
Yehea I. Ismail, Eby G. Friedman, José Luis Neves
1998 A conf
Power dissipated by CMOS gates driving lossless transmission lines.
ISLPED
Yehea I. Ismail, Eby G. Friedman, José Luis Neves
1998 — conf
Transient power in CMOS gates driving LC transmission lines.
ICECS
Yehea I. Ismail, Eby G. Friedman, José Luis Neves
1997 J jnl
Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations.
J. VLSI Signal Process.
José Luis Neves, Eby G. Friedman
1997 J jnl
High Performance Clock Distribution Networks.
J. VLSI Signal Process.
Eby G. Friedman
1997 J jnl
Incorporating interconnect, register, and clock distribution delays into the retiming process.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.
1997 J jnl
Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits.
J. VLSI Signal Process.
Kris Gaj, Eby G. Friedman, Marc J. Feldman
1996 J jnl
Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew.
IEEE Trans. Very Large Scale Integr. Syst.
José Luis Neves, Eby G. Friedman
1996 A* conf
Optimal Clock Skew Scheduling Tolerant to Process Variations.
DAC
José Luis Neves, Eby G. Friedman
1995 J jnl
A unified design methodology for CMOS tapered buffers.
IEEE Trans. Very Large Scale Integr. Syst.
Brian S. Cherkauer, Eby G. Friedman
1995 J jnl
Design of tapered buffers with local interconnect capacitance.
IEEE J. Solid State Circuits
Brian S. Cherkauer, Eby G. Friedman
1995 C conf
Minimizing Power Dissipation in Non-Zero Skew-Based Clock Distribution Networks.
ISCAS
José Luis Neves, Eby G. Friedman
1995 C conf
Monotonicity Constraints on Path Delays for Efficient Retiming with Localized Clock Skew and Variable Register Delay.
ISCAS
Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.
1994 J jnl
Channel width tapering of serially connected MOSFET's with emphasis on power dissipation.
IEEE Trans. Very Large Scale Integr. Syst.
Brian S. Cherkauer, Eby G. Friedman
1994 C conf
Circuit Synthesis of Clock Distribution Networks Based on Non-Zero Clock Skew.
ISCAS
José Luis Neves, Eby G. Friedman
1994 C conf
Forum: From 100 Milliwatts/MIPS to 10 Microwatts/MIPS.
ISCAS
Eby G. Friedman, Sung-Mo Kang, Eric A. Vittoz, David J. Allstot, Erik P. Harris, Ran-Hong Yan
1994 A conf
Retiming with non-zero clock skew, variable register, and interconnect delay.
ICCAD
Tolga Soyata, Eby G. Friedman
1994 C conf
Unification of Speed, Power, Area & Reliability in CMOS Tapered Buffer Design.
ISCAS
Brian S. Cherkauer, Eby G. Friedman
1993 C conf
Clock Distribution Design in VLSI Circuits. An Overview.
ISCAS
Eby G. Friedman
1993 C conf
Integration of Clock Skew and Register Delays into a Retiming Algorithm.
ISCAS
Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.
1993 C conf
The Effects of Channel Width Tapering on the Power Dissipation of Serially Connected MOSFETs.
ISCAS
Brian S. Cherkauer, Eby G. Friedman
1991 J jnl
Clock frequency and latency in synchronous digital systems.
IEEE Trans. Signal Process.
Eby G. Friedman, James H. Mulligan Jr.