Ebru Aydin Gol

53 papers A* 1A 1C 5Journal 25Unranked 21

Year	Rank	Type	Title / Venue / Authors
2025	A*	`conf`	Interchangeable Token Embeddings for Extendable Vocabulary and Alpha-Equivalence. ICML Ilker Isik, Ramazan Gokberk Cinbis, Ebru Aydin Gol
2024	J	`jnl`	Cycle encoding-based parameter synthesis for timed automata safety. Acta Informatica Burkay Sucu, Ebru Aydin Gol
2024	J	`jnl`	Field Teams Coordination for Earthquake-Damaged Distribution System Energization. CoRR Ilker Isik, Ebru Aydin Gol
2024	J	`jnl`	Field teams coordination for earthquake-damaged distribution system energization. Reliab. Eng. Syst. Saf. Ilker Isik, Ebru Aydin Gol
2024	J	`jnl`	Interchangeable Token Embeddings for Extendable Vocabulary and Alpha-Equivalence. CoRR Ilker Isik, Ramazan Gokberk Cinbis, Ebru Aydin Gol
2024	J	`jnl`	Learning to Estimate System Specifications in Linear Temporal Logic using Transformers and Mamba. CoRR Ilker Isik, Ebru Aydin Gol, Ramazan Gokberk Cinbis
2024	J	`jnl`	Optimal Policy Synthesis from A Sequence of Goal Sets with An Application to Electric Distribution System Restoration. CoRR Ilker Isik, Onur Yigit Arpali, Ebru Aydin Gol
2022	J	`jnl`	An automated system repair framework with signal temporal logic. Acta Informatica Mert Ergurtuna, Beyazit Yalcinkaya, Ebru Aydin Gol
2022	J	`jnl`	Timed Automata Robustness Analysis via Model Checking. Log. Methods Comput. Sci. Jaroslav Bendík, Ahmet Sencan, Ebru Aydin Gol, Ivana Cerná
2022	—	`conf`	Traffic Prediction with Peak-Aware Temporal Graph Convolutional Networks. SIU Fatih Acun, Sinan Kalkan, Ebru Aydin Gol
2021	—	`conf`	Control Synthesis for Parametric Timed Automata under Unavoidability Specifications. ECC Ebru Aydin Gol
2021	J	`jnl`	Control Synthesis for Parametric Timed Automata under Unavoidability Specifications. CoRR Ebru Aydin Gol
2021	—	`conf`	Optimal Policy Synthesis from A Sequence of Goal Sets with An Application to Electric Distribution System Restoration. ADHS Ilker Isik, Onur Yigit Arpali, Ebru Aydin Gol
2021	—	`conf`	Timed Automata Relaxation for Reachability. TACAS (1) Jaroslav Bendík, Ahmet Sencan, Ebru Aydin Gol, Ivana Cerná
2021	J	`jnl`	Timed Automata Robustness Analysis via Model Checking. CoRR Jaroslav Bendík, Ahmet Sencan, Ebru Aydin Gol, Ivana Cerná
2021	—	`conf`	Traffic Prediction on Large Scale Traffic Networks Using ARIMA and K-Means. SIU Fatih Acun, Ebru Aydin Gol
2020	—	`conf`	Classification of Time-Series Data using ptSTL. SIU Mert Ergürtuna, Ebru Aydin Gol
2020	J	`jnl`	Kontrol Edilebilir ptSTL Formulu Sentezi - Synthesis of Controllable ptSTL Formulas. CoRR Irmak Saglam, Ebru Aydin Gol
2020	—	`conf`	Learning Parameters of ptSTL Formulas with Backpropagation. SIU Ahmet Ketenci, Ebru Aydin Gol
2020	—	`conf`	Synthesis of Controllable ptSTL Formulas. SIU Irmak Saglam, Ebru Aydin Gol
2020	J	`jnl`	Synthesis of Monitoring Rules with STL. J. Circuits Syst. Comput. Sertaç Kagan Aydin, Ebru Aydin Gol
2019	—	`conf`	A Novel MDP Based Decision Support Framework to Restore Earthquake Damaged Distribution Systems. ISGT Europe Ebru Aydin Gol, Burcu Güldür Erkal, Murat Göl
2019	J	`jnl`	A Novel MDP Based Decision Support Framework to Restore Earthquake Damaged Distribution Systems. CoRR Ebru Aydin Gol, Burcu Güldür Erkal, Murat Göl
2019	J	`jnl`	ATAC: A Tool for Automating Timed Automata Construction. CoRR Beyazit Yalcinkaya, Ebru Aydin Gol
2019	J	`jnl`	An Efficient Formula Synthesis Method with Past Signal Temporal Logic. CoRR Mert Ergurtuna, Ebru Aydin Gol
2019	—	`conf`	Cause Mining and Controller Synthesis with STL. CDC Irmak Saglam, Ebru Aydin Gol
2019	J	`jnl`	Cause Mining and Controller Synthesis with STL. CoRR Irmak Saglam, Ebru Aydin Gol
2019	—	`conf`	Clock reduction in timed automata while preserving design parameters. FormaliSE@ICSE Beyazit Yalcinkaya, Ebru Aydin Gol
2019	C	`conf`	Synthesis of Monitoring Rules via Data Mining. ACC Ahmet Ketenci, Ebru Aydin Gol
2018	J	`jnl`	A Formal Methods Approach to Pattern Recognition and Synthesis in Reaction Diffusion Networks. IEEE Trans. Control. Netw. Syst. Ezio Bartocci, Ebru Aydin Gol, Iman Haghighi, Calin Belta
2018	C	`conf`	Efficient Online Monitoring and Formula Synthesis with Past STL. CoDIT Ebru Aydin Gol
2018	C	`conf`	Formal Control of Traffic Systems via Network Decomposition. ACC Kemal Cagri Bardakci, Ebru Aydin Gol
2018	—	`conf`	On the use of genetic algorithms for synthesis of signal temporal logic formulas. SIU Sertaç Kagan Aydin, Ebru Aydin Gol
2017	—	`conf`	Synthesis of formal control strategies for traffic networks via partitioning. SIU Kemal Cagri Bardakci, Ebru Aydin Gol
2016	J	`jnl`	Traffic Network Control From Temporal Logic Specifications. IEEE Trans. Control. Netw. Syst. Samuel Coogan, Ebru Aydin Gol, Murat Arcak, Calin Belta
2015	C	`conf`	Controlling a network of signalized intersections from temporal logical specifications. ACC Samuel Coogan, Ebru Aydin Gol, Murat Arcak, Calin Belta
2015	J	`jnl`	Temporal logic model predictive control. Autom. Ebru Aydin Gol, Mircea Lazar, Calin Belta
2014	J	`jnl`	A Formal Methods Approach to Pattern Synthesis in Reaction Diffusion Systems. CoRR Ebru Aydin Gol, Ezio Bartocci, Calin Belta
2014	—	`conf`	A formal methods approach to pattern synthesis in reaction diffusion systems. CDC Ebru Aydin Gol, Ezio Bartocci, Calin Belta
2014	C	`conf`	An additive cost approach to optimal Temporal Logic control. ACC Ebru Aydin Gol, Calin Belta
2014	J	`jnl`	Finite Bisimulations for Switched Linear Systems. IEEE Trans. Autom. Control. Ebru Aydin Gol, Xu Chu Ding, Mircea Lazar, Calin Belta
2014	J	`jnl`	Language-Guided Controller Synthesis for Linear Systems. IEEE Trans. Autom. Control. Ebru Aydin Gol, Mircea Lazar, Calin Belta
2014	—	`conf`	Temporal logic inference for classification and prediction from data. HSCC Zhaodan Kong, Austin Jones, Ana Medina Ayala, Ebru Aydin Gol, Calin Belta
2014	J	`jnl`	Traffic Network Control from Temporal Logic Specifications. CoRR Samuel Coogan, Ebru Aydin Gol, Murat Arcak, Calin Belta
2013	—	`conf`	Data-driven verification of synthetic gene networks. CDC Ebru Aydin Gol, Douglas Densmore, Calin Belta
2013	—	`conf`	Temporal logic model predictive control for discrete-time systems. HSCC Ebru Aydin Gol, Mircea Lazar
2012	A	`conf`	Experimentally driven verification of synthetic biological circuits. DATE Boyan Yordanov, Evan Appleton, Rishi Ganguly, Ebru Aydin Gol, Swati Banerjee Carr, Swapnil Bhatia, Traci Haddock, Calin Belta, Douglas Densmore
2012	J	`jnl`	Finite Bisimulations for Switched Linear Systems CoRR Ebru Aydin Gol, Xu Chu Ding, Mircea Lazar, Calin Belta
2012	—	`conf`	Finite bisimulations for switched linear systems. CDC Ebru Aydin Gol, Xu Chu Ding, Mircea Lazar, Calin Belta
2012	—	`conf`	Language-guided controller synthesis for discrete-time linear systems. HSCC Ebru Aydin Gol, Mircea Lazar, Calin Belta
2012	J	`jnl`	Time-Constrained Temporal Logic Control of Multi-Affine Systems CoRR Ebru Aydin Gol, Calin Belta
2012	—	`conf`	Time-Constrained Temporal Logic Control of Multi-Affine Systems. ADHS Ebru Aydin Gol, Calin Belta
2011	—	`conf`	Locomotion Gait Optimization For Modular Robots; Coevolving Morphology and Control. FET Soha Pouya, Ebru Aydin Gol, Rico Möckel, Auke Jan Ijspeert