Earl E. Swartzlander Jr.

232 papers A* 1A 1B 4C 39Misc 20Journal 90Unranked 70

Year	Rank	Type	Title / Venue / Authors
2023	C	`conf`	Improved Montgomery Multiplication. ARITH Trenton J. Grale, Earl E. Swartzlander Jr.
2022	—	`conf`	LogGen: A Parameterized Generator for Designing Floating-Point Logarithm Units for Deep Learning. ISQED Pragnesh Patel, Aman Arora, Earl E. Swartzlander Jr., Lizy K. John
2020	—	`conf`	A Bfloat16 Fused Multiplier-Adder. UEMCON Stafford Hutchins, Earl E. Swartzlander Jr.
2019	Misc	`conf`	A Variable-Latency Architecture for Accelerating Deterministic Approaches to Stochastic Computing. ACSSC Alexander J. Groszewski, Earl E. Swartzlander Jr.
2019	J	`jnl`	Design and Analysis of Approximate Redundant Binary Multipliers. IEEE Trans. Computers Weiqiang Liu, Tian Cao, Peipei Yin, Yuying Zhu, Chenghua Wang, Earl E. Swartzlander Jr., Fabrizio Lombardi
2019	—	`ch.`	Memristor-Based Addition and Multiplication. Handbook of Memristor Networks K'Andrea C. Bickerstaff, Earl E. Swartzlander Jr.
2019	—	`conf`	Parallel GF(2 MWSCAS Trenton J. Grale, Earl E. Swartzlander Jr.
2018	J	`jnl`	Data Compression Device Based on Modified LZ4 Algorithm. IEEE Trans. Consumer Electron. Weiqiang Liu, Faqiang Mei, Chenghua Wang, Máire O'Neill, Earl E. Swartzlander Jr.
2018	J	`jnl`	Design of High-Speed Wide-Word Hybrid Parallel-Prefix/Carry-Select and Skip Adders. J. Signal Process. Syst. Xiao-Ping Cui, Weiqiang Liu, Shumin Wang, Earl E. Swartzlander Jr., Fabrizio Lombardi
2018	J	`jnl`	Designs of Approximate Floating-Point Multipliers with Variable Accuracy for Error-Tolerant Applications. J. Signal Process. Syst. Peipei Yin, Chenghua Wang, Weiqiang Liu, Earl E. Swartzlander Jr., Fabrizio Lombardi
2018	—	`conf`	Memristor Adder Design. MWSCAS Nagaraja Revanna, Earl E. Swartzlander Jr.
2018	J	`jnl`	Memristor-Based Computing. IEEE Micro Lizy K. John, Earl E. Swartzlander Jr.
2017	—	`conf`	Dadda Multiplier designs using memristors. ICICDT Lauren Guckert, Earl E. Swartzlander Jr.
2017	J	`jnl`	Guest Editorial: Introduction to the Special Issue on Emerging Technologies and Designs for Application-Specific Computing. IEEE Trans. Emerg. Top. Comput. Weiqiang Liu, Earl E. Swartzlander Jr., Máire O'Neill
2017	J	`jnl`	High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes. IEEE Trans. Computers Xiao-Ping Cui, Wenwen Dong, Weiqiang Liu, Earl E. Swartzlander Jr., Fabrizio Lombardi
2017	J	`jnl`	MAD Gates - Memristor Logic Design Using Driver Circuitry. IEEE Trans. Circuits Syst. II Express Briefs Lauren Guckert, Earl E. Swartzlander Jr.
2017	J	`jnl`	Optimized Memristor-Based Multipliers. IEEE Trans. Circuits Syst. I Regul. Pap. Lauren Guckert, Earl E. Swartzlander Jr.
2017	Misc	`conf`	Parallel GF(2 ACSSC Trenton J. Grale, Earl E. Swartzlander Jr.
2017	Misc	`conf`	The future of computing - Arithmetic circuits implemented with memristors. ACSSC Nagaraja Revanna, Lauren Guckert, Earl E. Swartzlander Jr.
2016	J	`jnl`	A Fused Floating-Point Four-Term Dot Product Unit. IEEE Trans. Circuits Syst. I Regul. Pap. Jongwook Sohn, Earl E. Swartzlander Jr.
2016	J	`jnl`	A Modified Partial Product Generator for Redundant Binary Multipliers. IEEE Trans. Computers Xiao-Ping Cui, Weiqiang Liu, Xin Chen, Earl E. Swartzlander Jr., Fabrizio Lombardi
2016	—	`conf`	Arithmetic circuit design with memristor based high fan-out logic gates. UEMCON Nagaraja Revanna, Earl E. Swartzlander Jr.
2016	Misc	`conf`	Memristor based adder circuit design. ACSSC Nagaraja Revanna, Earl E. Swartzlander Jr.
2016	Misc	`conf`	Optimized memristor-based ripple carry adders. ACSSC Lauren Guckert, Earl E. Swartzlander Jr.
2015	J	`jnl`	Design of 3-D quantum-dot cellular automata adders. IEICE Electron. Express Weiqiang Liu, Earl E. Swartzlander Jr.
2015	Misc	`conf`	Exploiting asymmetry in Booth-encoded multipliers for reduced energy multiplication. ACSSC Mike O'Connor, Earl E. Swartzlander Jr.
2015	Misc	`conf`	Extreme multi-core, multi-network Java DataFlow Machine (JavaFlow). ACSSC Robert J. Ascott, Earl E. Swartzlander Jr.
2015	C	`conf`	Low-Cost Duplicate Multiplication. ARITH Michael B. Sullivan, Earl E. Swartzlander Jr.
2014	J	`jnl`	A Fused Floating-Point Three-Term Adder. IEEE Trans. Circuits Syst. I Regul. Pap. Jongwook Sohn, Earl E. Swartzlander Jr.
2014	J	`jnl`	Design of Goldschmidt Dividers with Quantum-Dot Cellular Automata. IEEE Trans. Computers Inwook Kong, Seong-Wan Kim, Earl E. Swartzlander Jr.
2014	—	`ch.`	High-Speed Computer Arithmetic. Computing Handbook, 3rd ed. (1) Earl E. Swartzlander Jr.
2014	Misc	`conf`	Improved non-restoring square root algorithm with dual path calculation. ACSSC Kihwan Jun, Earl E. Swartzlander Jr.
2014	Misc	`conf`	Memristor based adders. ACSSC Divya Mahajan, Matheen Musaddiq, Earl E. Swartzlander Jr.
2014	—	`ch.`	Security Issues in QCA Circuit Design - Power Analysis Attacks. Field-Coupled Nanocomputing Weiqiang Liu, Saket Srivastava, Máire O'Neill, Earl E. Swartzlander Jr.
2013	—	`conf`	Fused floating-point magnitude unit. MWSCAS Jae Hong Min, Earl E. Swartzlander Jr.
2013	—	`conf`	Fused floating-point two-term sum-of-squares unit. ASAP Jae Hong Min, Earl E. Swartzlander Jr.
2013	Misc	`conf`	Implementation of a high speed multiplier using carry lookahead adders. ACSSC Wesley Chu, Ali I. Unwala, Pohan Wu, Earl E. Swartzlander Jr.
2013	C	`conf`	Improved Architectures for a Floating-Point Fused Dot Product Unit. IEEE Symposium on Computer Arithmetic Jongwook Sohn, Earl E. Swartzlander Jr.
2013	—	`conf`	Improved non-restoring division algorithm with dual path calculation. MWSCAS Kihwan Jun, Earl E. Swartzlander Jr.
2013	Misc	`conf`	On separable error detection for addition. ACSSC Michael B. Sullivan, Earl E. Swartzlander Jr.
2013	C	`conf`	Power analysis attack of QCA circuits: A case study of the Serpent cipher. ISCAS Weiqiang Liu, Saket Srivastava, Liang Lu, Máire O'Neill, Earl E. Swartzlander Jr.
2013	J	`jnl`	QCA Systolic Array Design. IEEE Trans. Computers Liang Lu, Weiqiang Liu, Máire O'Neill, Earl E. Swartzlander Jr.
2013	J	`jnl`	STARS: Electronic Calculators: Desktop to Pocket. Proc. IEEE Earl E. Swartzlander Jr.
2013	J	`jnl`	Structure-Aware Placement Techniques for Designs With Datapaths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan
2013	—	`conf`	The optimum Booth radix for low power integer multipliers. IDT Hani H. Saleh, Baker S. Mohammad, Earl E. Swartzlander Jr.
2013	C	`conf`	Truncated Logarithmic Approximation. IEEE Symposium on Computer Arithmetic Michael B. Sullivan, Earl E. Swartzlander Jr.
2012	—	`conf`	A low-power dual-path floating-point fused add-subtract unit. ACSCC Jae Hong Min, Jongwook Sohn, Earl E. Swartzlander Jr.
2012	J	`jnl`	A new hierarchical packet classification algorithm. Comput. Networks Hyesook Lim, Soohyun Lee, Earl E. Swartzlander Jr.
2012	—	`conf`	A review of QCA adders and metrics. ACSCC Weiqiang Liu, Máire O'Neill, Earl E. Swartzlander Jr.
2012	C	`conf`	Cost-efficient decimal adder design in Quantum-dot cellular automata. ISCAS Weiqiang Liu, Liang Lu, Máire O'Neill, Earl E. Swartzlander Jr.
2012	J	`jnl`	FFT Implementation with Fused Floating-Point Operations. IEEE Trans. Computers Earl E. Swartzlander Jr., Hani H. Saleh
2012	—	`conf`	Hybrid Han-Carlson adder. MWSCAS Sreenivaas Muthyala Sudhakar, Kumar P. Chidambaram, Earl E. Swartzlander Jr.
2012	J	`jnl`	Improved Architectures for a Fused Floating-Point Add-Subtract Unit. IEEE Trans. Circuits Syst. I Regul. Pap. Jongwook Sohn, Earl E. Swartzlander Jr.
2012	—	`conf`	Keep it straight: teaching placement how to better handle designs with datapaths. ISPD Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan
2012	—	`conf`	Long Residue Checking for Adders. ASAP Michael B. Sullivan, Earl E. Swartzlander Jr.
2012	—	`conf`	Modified non-restoring division algorithm with improved delay profile and error correction. ACSCC Kihwan Jun, Earl E. Swartzlander Jr.
2012	—	`conf`	Truncated error correction for flexible approximate multiplication. ACSCC Michael B. Sullivan, Earl E. Swartzlander Jr.
2011	—	`ed.`	22nd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2011, Santa Monica, CA, USA, Sept. 11-14, 2011 ASAP Joseph R. Cavallaro, Milos D. Ercegovac, Frank Hannig, Paolo Ienne, Earl E. Swartzlander Jr., Alexandre F. Tenca
2011	J	`jnl`	A Goldschmidt Division Method With Faster Than Quadratic Convergence. IEEE Trans. Very Large Scale Integr. Syst. Inwook Kong, Earl E. Swartzlander Jr.
2011	—	`conf`	A floating-point fused FFT butterfly arithmetic unit with Merged Multiple-Constant Multipliers. ACSCC Jae Hong Min, Seong-Wan Kim, Earl E. Swartzlander Jr.
2011	C	`conf`	Design rules for Quantum-dot Cellular Automata. ISCAS Weiqiang Liu, Liang Lu, Máire O'Neill, Earl E. Swartzlander Jr.
2011	—	`conf`	Hybrid residue generators for increased efficiency. ACSCC Michael B. Sullivan, Earl E. Swartzlander Jr.
2011	—	`conf`	Quantifying academic placer performance on custom designs. ISPD Samuel I. Ward, David A. Papa, Zhuo Li, Cliff N. Sze, Charles J. Alpert, Earl E. Swartzlander Jr.
2011	—	`conf`	The fully-serial pipelined multiplier. ACSCC Andrew G. Shafer, Lyndsi R. Parker, Earl E. Swartzlander Jr.
2011	J	`jnl`	Tunable Mismatch Shaping for Quadrature Bandpass Delta-Sigma Data Converters. J. Signal Process. Syst. Waqas Akram, Earl E. Swartzlander Jr.
2010	J	`jnl`	A Reduced Complexity Wallace Multiplier Reduction. IEEE Trans. Computers Ron S. Waters, Earl E. Swartzlander Jr.
2010	J	`jnl`	A Rounding Method to Reduce the Required Multiplier Precision for Goldschmidt Division. IEEE Trans. Computers Inwook Kong, Earl E. Swartzlander Jr.
2010	Misc	`conf`	A novel technique for tunable mismatch shaping in oversampled digital-to-analog converters. ICASSP Waqas Akram, Earl E. Swartzlander Jr.
2010	J	`jnl`	Adaptive CORDIC: Using Parallel Angle Recoding to Accelerate Rotations. IEEE Trans. Computers Terence K. Rodrigues, Earl E. Swartzlander Jr.
2010	—	`conf`	High speed recursion-free CORDIC architecture. SoCC Shakeel S. Abdulla, Haewoon Nam, Earl E. Swartzlander Jr., Jacob A. Abraham
2010	J	`jnl`	Priority Tries for IP Address Lookup. IEEE Trans. Computers Hyesook Lim, Changhoon Yim, Earl E. Swartzlander Jr.
2010	—	`conf`	QCA Systolic Matrix Multiplier. ISVLSI Liang Lu, Weiqiang Liu, Máire O'Neill, Earl E. Swartzlander Jr.
2009	—	`conf`	A Power-Scalable Switch-Based Multi-processor FFT. ASAP Bassam Jamil Mohd, Earl E. Swartzlander Jr.
2009	—	`conf`	ASIC evaluation of ECHO hash function. SoCC Liang Lu, Máire O'Neill, Earl E. Swartzlander Jr.
2009	J	`jnl`	Adder and Multiplier Design in Quantum-Dot Cellular Automata. IEEE Trans. Computers Heumpil Cho, Earl E. Swartzlander Jr.
2009	—	`conf`	Design of a Goldschmidt iterative divider for quantum-dot cellular automata. NANOARCH Inwook Kong, Earl E. Swartzlander Jr., Seong-Wan Kim
2009	—	`conf`	JavaFlow - A Java dataflow machine. SoCC Robert J. Ascott, Earl E. Swartzlander Jr.
2008	Misc	`conf`	32 bit single cycle nonlinear VLSI cell for the ICA algorithm. ICASSP Vijay K. Jain, Earl E. Swartzlander Jr.
2008	C	`conf`	A floating-point fused dot-product unit. ICCD Hani H. Saleh, Earl E. Swartzlander Jr.
2008	—	`conf`	A rounding method with improved error tolerance for division by convergence. ACSCC Inwook Kong, Earl E. Swartzlander Jr.
2008	J	`jnl`	Bridge Floating-Point Fused Multiply-Add Design. IEEE Trans. Very Large Scale Integr. Syst. Eric Quinnell, Earl E. Swartzlander Jr., Carl Lemonds
2008	—	`ch.`	Fixed-Point Computer Arithmetic. Wiley Encyclopedia of Computer Science and Engineering Earl E. Swartzlander Jr.
2008	—	`ch.`	Floating-Point Computer Arithmetic. Wiley Encyclopedia of Computer Science and Engineering Eric Quinnell, Earl E. Swartzlander Jr.
2008	—	`conf`	Fused floating-point arithmetic for DSP. ACSCC Earl E. Swartzlander Jr., Hani H. Saleh
2008	—	`conf`	High performance IP lookup circuit using DDR SDRAM. SoCC Xin Yang, Jun Mu, Sakir Sezer, John V. McCanny, Earl E. Swartzlander Jr.
2008	J	`jnl`	Negative Save Sign Extension for Multi-term Adders and Multipliers. J. Signal Process. Syst. Robert T. Grisamore, Earl E. Swartzlander Jr.
2008	J	`jnl`	Speculative Carry Generation With Prefix Adder. IEEE Trans. Very Large Scale Integr. Syst. Youngmoon Choi, Earl E. Swartzlander Jr.
2008	J	`jnl`	Systolic FFT Processors: A Personal Perspective. J. Signal Process. Syst. Earl E. Swartzlander Jr.
2007	C	`conf`	Contention-free switch-based implementation of 1024-point Radix-2 Fourier Transform Engine. ICCD Hani Saleh, Bassam Jamil Mohd, Adnan Aziz, Earl E. Swartzlander Jr.
2007	C	`conf`	Serial Parallel Multiplier Design in Quantum-dot Cellular Automata. IEEE Symposium on Computer Arithmetic Heumpil Cho, Earl E. Swartzlander Jr.
2007	—	`conf`	The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm. VLSI-SoC (Selected Papers) Bassam Jamil Mohd, Earl E. Swartzlander Jr., Adnan Aziz
2007	J	`jnl`	The Negative Two's Complement Number System. J. VLSI Signal Process. Earl E. Swartzlander Jr.
2007	C	`conf`	The hazard-free superscalar pipeline fast fourier transform algorithm and architecture. VLSI-SoC Bassam Jamil Mohd, Adnan Aziz, Earl E. Swartzlander Jr.
2006	—	`conf`	Design of Radix-4 SRT Dividers in 65 Nanometer CMOS Technology. ASAP Tung N. Pham, Earl E. Swartzlander Jr.
2006	J	`jnl`	Digit-pipelined direct digital frequency synthesis based on differential CORDIC. IEEE Trans. Circuits Syst. I Regul. Pap. Chang Yong Kang, Earl E. Swartzlander Jr.
2006	—	`conf`	Systolic FFT Processors: Past, Present and Future. ASAP Earl E. Swartzlander Jr.
2005	—	`conf`	Multiply-Accumulate Architecture for a Special Class of Optimal Extension Fields. ASAP Moboluwaji O. Sanu, Earl E. Swartzlander Jr.
2005	C	`conf`	Parallel Prefix Adder Design with Matrix Representation. IEEE Symposium on Computer Arithmetic Youngmoon Choi, Earl E. Swartzlander Jr.
2005	—	`conf`	Three Dimensional System on Chip Technology, invited. IWSOC Earl E. Swartzlander Jr.
2004	—	`conf`	A Review of Large Parallel Counter Designs. ISVLSI Earl E. Swartzlander Jr.
2004	—	`conf`	Parallel Montgomery Multipliers. ASAP Moboluwaji O. Sanu, Earl E. Swartzlander Jr., Craig M. Chase
2003	—	`conf`	A self-testing method for the pipelined A/D converter. ISCAS (1) Jaeki Yoo, Edward Lee, Earl E. Swartzlander Jr.
2003	—	`conf`	An Architecture for a Radix-4 Modular Pipeline Fast Fourier Transform. ASAP Ayman M. El-Khashab, Earl E. Swartzlander Jr.
2003	J	`jnl`	Guest Editorial. J. VLSI Signal Process. Mohammad Ibrahim, Earl E. Swartzlander Jr.
2003	—	`conf`	Quadruple Time Redundancy Adders. DFT Whitney J. Townsend, Jacob A. Abraham, Earl E. Swartzlander Jr.
2002	J	`jnl`	A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells. J. VLSI Signal Process. Ohsang Kwon, Kevin J. Nowka, Earl E. Swartzlander Jr.
2002	J	`jnl`	A scaled DCT architecture with the CORDIC algorithm. IEEE Trans. Signal Process. Sungwook Yu, Earl E. Swartzlander Jr.
2002	—	`conf`	An Analysis of the CORDIC Algorithm for Direct Digital Frequency Synthesis. ASAP Chang Yong Kang, Earl E. Swartzlander Jr.
2002	—	`conf`	Implementation of a Single Chip, Pipelined, Complex, One-Dimensional Fast FourierTransform in 0.25 mu m BulkCMOS. ASAP Steven M. Currie, Paul R. Schumacher, Barry K. Gilbert, Earl E. Swartzlander Jr., Barbara A. Randall
2001	—	`conf`	A fast hybrid carry-lookahead/carry-select adder design. ACM Great Lakes Symposium on VLSI Ohsang Kwon, Earl E. Swartzlander Jr., Kevin J. Nowka
2001	J	`jnl`	A pipelined architecture for the multidimensional DFT. IEEE Trans. Signal Process. Sungwook Yu, Earl E. Swartzlander Jr.
2001	C	`conf`	Analysis of Column Compression Multipliers. IEEE Symposium on Computer Arithmetic K'Andrea C. Bickerstaff, Earl E. Swartzlander Jr., Michael J. Schulte
2001	J	`jnl`	DCT Implementation with Distributed Arithmetic. IEEE Trans. Computers Sungwook Yu, Earl E. Swartzlander Jr.
2001	—	`conf`	Enhanced Concurrent Error Correcting Arithmetic Unit Design Using Alternating Logic. DFT Tat Ngai, Earl E. Swartzlander Jr., Chen He
2001	Misc	`conf`	Time-shared TMR for fault-tolerant CORDIC processors. ICASSP Jae-Hyuck Kwak, Vincenzo Piuri, Earl E. Swartzlander Jr.
2000	—	`conf`	A 16-Bit x 16-Bit MAC Design Using Fast 5: 2 Compressors. ASAP Ohsang Kwon, Earl E. Swartzlander Jr., Kevin J. Nowka
2000	J	`jnl`	A Family of Variable-Precision Interval Arithmetic Processors. IEEE Trans. Computers Michael J. Schulte, Earl E. Swartzlander Jr.
2000	J	`jnl`	A Serial-Parallel Architecture for Two-Dimensional Discrete Cosine and Inverse Discrete Cosine Transforms. IEEE Trans. Computers Hyesook Lim, Vincenzo Piuri, Earl E. Swartzlander Jr.
2000	—	`conf`	Fault-Tolerant High-Performance Cordic Processors. DFT Jae-Hyuck Kwak, Earl E. Swartzlander Jr., Vincenzo Piuri
2000	J	`jnl`	Fault-Tolerant Newton-Raphson and Goldschmidt Dividers Using Time Shared TMR. IEEE Trans. Computers W. Lynn Gallagher, Earl E. Swartzlander Jr.
2000	J	`jnl`	High-Speed CORDIC Based on an Overlapped Architecture and a Novel sigma-Prediction Method. J. VLSI Signal Process. Jae-Hyuck Kwak, Jae Hun Choi, Earl E. Swartzlander Jr.
1999	J	`jnl`	A parallel implementation of the 2-D discrete wavelet transform without interprocessor communications. IEEE Trans. Signal Process. Francescomaria Marino, Vincenzo Piuri, Earl E. Swartzlander Jr.
1999	—	`conf`	Bipolar merged arithmetic for wavelet architectures. ISCAS (3) Gwangwoo Choe, Earl E. Swartzlander Jr.
1999	C	`conf`	High-Speed CORDIC Architecture Based on Redundant Sum Formation and Overlapped s-Selection. ICCD Jae Hun Choi, Jae-Hyuck Kwak, Earl E. Swartzlander Jr.
1999	J	`jnl`	Multidimensional systolic arrays for the implementation of discrete Fourier transforms. IEEE Trans. Signal Process. Hyesook Lim, Earl E. Swartzlander Jr.
1999	J	`jnl`	Parallel Implementation of Multidimensional Transforms without Interprocessor Communication. IEEE Trans. Computers Francescomaria Marino, Earl E. Swartzlander Jr.
1999	—	`conf`	Power Consumption in Fast Dividers Using Time Shared TMR. DFT W. Lynn Gallagher, Earl E. Swartzlander Jr.
1999	—	`conf`	Time-Shared Modular Redundancy for Fault-Tolerant FFT Processors. DFT Vincenzo Piuri, Earl E. Swartzlander Jr.
1998	C	`conf`	A reduction scheme to optimize the Wallace multiplier. ICCD Moises E. Robinson, Earl E. Swartzlander Jr.
1998	J	`jnl`	Calculators. IEEE Ann. Hist. Comput. Earl E. Swartzlander Jr.
1998	J	`jnl`	Calculators. IEEE Ann. Hist. Comput. Earl E. Swartzlander Jr.
1998	J	`jnl`	Editorial Message. J. VLSI Signal Process. Mary Jane Irwin, Sun-Yuan Kung, Earl E. Swartzlander Jr.
1998	—	`conf`	Error-Correcting Goldschmidt Dividers Using Time Shared TMR. DFT W. Lynn Gallagher, Earl E. Swartzlander Jr.
1998	—	`conf`	Merged Arithmetic for Computing Wavelet Transforms. Great Lakes Symposium on VLSI Gwangwoo Choe, Earl E. Swartzlander Jr.
1998	J	`jnl`	VLSI, MCM, and WSI: A Design Comparison. IEEE Des. Test Comput. Earl E. Swartzlander Jr.
1997	J	`jnl`	Calculators. IEEE Ann. Hist. Comput. Earl E. Swartzlander Jr.
1997	—	`conf`	Fast Error-Correcting Newton-Raphson Dividers Using Time Shared TMR. DFT W. Lynn Gallagher, Earl E. Swartzlander Jr.
1997	—	`ch.`	High-Speed Computer Arithmetic. The Computer Science and Engineering Handbook Earl E. Swartzlander Jr.
1997	J	`jnl`	Hybrid CORDIC Algorithms. IEEE Trans. Computers Shaoyun Wang, Vincenzo Piuri, Earl E. Swartzlander Jr.
1997	C	`conf`	Power-Delay Characteristics of CMOS Multipliers. IEEE Symposium on Computer Arithmetic Thomas K. Callaway, Earl E. Swartzlander Jr.
1997	—	`conf`	Realization of a nonlinear digital filter on a DSP array processor. ASAP Hercule Kwan, Edward J. Powers, Earl E. Swartzlander Jr.
1997	A	`conf`	Survey of low power techniques for ROMs. ISLPED Edwin de Angel, Earl E. Swartzlander Jr.
1996	J	`jnl`	A new design for a lookahead carry generator. J. VLSI Signal Process. Hercule Kwan, Robert Leonard Nelson Jr., Earl E. Swartzlander Jr.
1996	J	`jnl`	Calculators. IEEE Ann. Hist. Comput. Earl E. Swartzlander Jr.
1996	J	`jnl`	Calculators. IEEE Ann. Hist. Comput. Earl E. Swartzlander Jr.
1996	—	`conf`	Comprehensive Modeling of VLSI Test. DFT Thomas A. Ziaja, Earl E. Swartzlander Jr.
1996	—	`conf`	Fault tolerant Newton-Raphson dividers using time shared TMR. DFT W. Lynn Gallagher, Earl E. Swartzlander Jr.
1996	—	`conf`	Finite Word-Length Effects Of An Unified Systolic Array For 2-D DCT/IDCT. ASAP Hyesook Lim, Changhoon Yim, Earl E. Swartzlander Jr.
1996	Misc	`conf`	Granularly-pipelined CORDIC processors for sine and cosine generators. ICASSP Shaoyun Wang, Vincenzo Piuri, Earl E. Swartzlander Jr.
1996	Misc	`conf`	Multidimensional systolic arrays for multidimensional DFTs. ICASSP Hyesook Lim, Earl E. Swartzlander Jr.
1996	J	`jnl`	Variable-precision, interval arithmetic coprocessors. Reliab. Comput. Michael J. Schulte, Earl E. Swartzlander Jr.
1995	—	`conf`	A Processor for Staggered Interval Arithmetic. ASAP Michael J. Schulte, Earl E. Swartzlander Jr.
1995	C	`conf`	A coprocessor for accurate and reliable numerical computations. ICCD Michael J. Schulte, Earl E. Swartzlander Jr.
1995	J	`jnl`	A software interface and hardware design for variable-precision interval arithmetic. Reliab. Comput. Michael J. Schulte, Earl E. Swartzlander Jr.
1995	C	`conf`	An efficient systolic array for the discrete cosine transform based on prime-factor decomposition . ICCD Hyesook Lim, Earl E. Swartzlander Jr.
1995	J	`jnl`	Calculators. IEEE Ann. Hist. Comput. Earl E. Swartzlander Jr.
1995	J	`jnl`	Calculators. IEEE Ann. Hist. Comput. Earl E. Swartzlander Jr.
1995	C	`conf`	Cascaded Implementation of an Iterative Inverse--Square--Root Algorithm, with Overflow Lookahead. IEEE Symposium on Computer Arithmetic Hercule Kwan, Robert Leonard Nelson Jr., Earl E. Swartzlander Jr.
1995	—	`conf`	Characterization and analysis of errors in circuit test. DFT Thomas A. Ziaja, Earl E. Swartzlander Jr.
1995	—	`conf`	Efficient time redundancy for error correcting inner-product units and convolvers. DFT Yuang-Ming Hsu, Vincenzo Piuri, Earl E. Swartzlander Jr.
1995	C	`conf`	Fault-Tolerant Neural Architectures: The Use of Rotated Operands. ISCAS Yuang-Ming Hsu, Vincenzo Piuri, Earl E. Swartzlander Jr.
1995	C	`conf`	Hardware Design and Arithmetic Algorithms for a Variable-Precision, Interval Arithmetic Coprocessor. IEEE Symposium on Computer Arithmetic Michael J. Schulte, Earl E. Swartzlander Jr.
1995	C	`conf`	Merged CORDIC Algorithm. ISCAS Shaoyun Wang, Earl E. Swartzlander Jr.
1995	J	`jnl`	Parallel reduced area multipliers. J. VLSI Signal Process. K'Andrea C. Bickerstaff, Michael J. Schulte, Earl E. Swartzlander Jr.
1995	C	`conf`	Rapid prototyping fault-tolerant heterogeneous digital signal processing systems. RSP Mohammad S. Khan, Earl E. Swartzlander Jr.
1995	—	`conf`	Recomputing by Operand Exchanging: A Time-redundancy Approach for Fault-tolerant Neural Networks. ASAP Yuang-Ming Hsu, Earl E. Swartzlander Jr., Vincenzo Piuri
1995	C	`conf`	Time-Redundant Multiple Computation for Fault-Tolerant Digital Neural Networks. ISCAS Yuang-Ming Hsu, Vincenzo Piuri, Earl E. Swartzlander Jr.
1994	C	`conf`	A New Asynchronous Multiplier Using Enable/Disable CMOS Differential Logic. ICCD Edwin de Angel, Earl E. Swartzlander Jr., Jacob A. Abraham
1994	C	`conf`	A Standardized Interface Control Unit for Heterogeneous Digital Signal Processors. ISCAS Mohammad S. Khan, Earl E. Swartzlander Jr.
1994	—	`conf`	A systolic array for 2-D DFT and 2-D DCT. ASAP Hyesook Lim, Earl E. Swartzlander Jr.
1994	—	`conf`	A variable-precision interval arithmetic processor. ASAP Michael J. Schulte, Earl E. Swartzlander Jr.
1994	J	`jnl`	Boundary scan in board manufacturing. J. Electron. Test. Thomas A. Ziaja, Earl E. Swartzlander Jr.
1994	J	`jnl`	Editorial. J. VLSI Signal Process. Earl E. Swartzlander Jr.
1994	J	`jnl`	Fast multiplier bit-product matrix reduction using bit-ordering and parity generation. J. VLSI Signal Process. Ben C. Drerup, Earl E. Swartzlander Jr.
1994	J	`jnl`	Hardware Designs for Exactly Rounded Elemantary Functions. IEEE Trans. Computers Michael J. Schulte, Earl E. Swartzlander Jr.
1994	B	`conf`	Heterogeneous Parallel Computing. ICPADS Earl E. Swartzlander Jr.
1994	B	`conf`	Is It Possible to Fairly Compare Interconnection Networks?. ICPADS José Duato, C. T. Howard Ho, Ferng-Ching Lin, Lionel M. Ni, Earl E. Swartzlander Jr.
1994	J	`jnl`	Optimal initial approximations for the Newton-Raphson division algorithm. Computing Michael J. Schulte, J. Omar, Earl E. Swartzlander Jr.
1994	J	`jnl`	Parallel counter implementation. J. VLSI Signal Process. Robert F. Jones, Earl E. Swartzlander Jr.
1994	—	`conf`	Reliability Estimation for Time Redundant Error Correcting Adders and Multipliers. DFT Yuang-Ming Hsu, Earl E. Swartzlander Jr.
1994	B	`conf`	Sorting Networks with Built-In Error Correction. ICPADS Yuang-Ming Hsu, Earl E. Swartzlander Jr.
1994	B	`conf`	What Types of Research Papers Should We Be Writing? ICPADS Thomas L. Casavant, Chi-Yuan Chin, Wen-Tsuen Chen, Kang G. Shin, Earl E. Swartzlander Jr., Joseph E. Urban
1993	C	`ed.`	11th Symposium on Computer Arithmetic, 29 June - 2 July 1993, Windsor, Canada, Proceedings. IEEE Symposium on Computer Arithmetic Earl E. Swartzlander Jr., Mary Jane Irwin, Graham A. Jullien
1993	C	`conf`	A Comparative Evaluation of Adders Based on Performance and Testability. ICCD Rathish Jayabharathi, Thomas Thomas, Earl E. Swartzlander Jr.
1993	C	`conf`	Design and implementation of an interface control unit for rapid prototyping. RSP Mohammad S. Khan, Earl E. Swartzlander Jr.
1993	C	`conf`	Estimating the power consumption of CMOS adders. IEEE Symposium on Computer Arithmetic Thomas K. Callaway, Earl E. Swartzlander Jr.
1993	C	`conf`	Exact rounding of certain elementary functions. IEEE Symposium on Computer Arithmetic Michael J. Schulte, Earl E. Swartzlander Jr.
1993	J	`jnl`	Modified Booth algorithm for high radix fixed-point multiplication. IEEE Trans. Very Large Scale Integr. Syst. Philip E. Madrid, Brian Millar, Earl E. Swartzlander Jr.
1993	J	`jnl`	Overlapped Subarray Segmentation: An Efficient Test Method for Cellular Arrays. VLSI Design Earl E. Swartzlander Jr., Miroslaw Malek
1993	—	`conf`	Reduced area multipliers. ASAP K'Andrea C. Bickerstaff, Michael J. Schulte, Earl E. Swartzlander Jr.
1993	C	`conf`	Superpipelined Adder Designs. ISCAS Ishaq H. Unwala, Earl E. Swartzlander Jr.
1993	—	`conf`	VLSI Concurrent Error Correcting Adders and Multipliers. DFT Yuang-Ming Hsu, Earl E. Swartzlander Jr.
1992	J	`jnl`	A Spanning Tree Carry Lookahead Adder. IEEE Trans. Computers Thomas W. Lynch, Earl E. Swartzlander Jr.
1992	J	`jnl`	A radix-8 wafer scale FFT processor. J. VLSI Signal Process. Earl E. Swartzlander Jr., Vijay K. Jain, Hiroomi Hikawa
1992	—	`conf`	Advanced technology for improved signal processor efficiency. ASAP Earl E. Swartzlander Jr.
1992	C	`conf`	Arithmetic Error Analysis of a new Reciprocal Cell. ICCD Vijay K. Jain, Gibert E. Perez, Earl E. Swartzlander Jr.
1992	—	`conf`	Implementation of Parallel Processors with Wafer Scale Integration. IPPS Thomas K. Callaway, Earl E. Swartzlander Jr.
1992	C	`conf`	Modified Booth Algorithm for High Radix Multiplication. ICCD Philip E. Madrid, Brian Millar, Earl E. Swartzlander Jr.
1992	J	`jnl`	Wafer-Scale Integration: Architectures and Algorithms - Guest Editors' Introduction. Computer W. Kent Fuchs, Earl E. Swartzlander Jr.
1991	C	`conf`	Arithmetic for digital neural networks. IEEE Symposium on Computer Arithmetic David Zhang, Graham A. Jullien, William C. Miller, Earl E. Swartzlander Jr.
1991	C	`conf`	High-speed multiplier design using multi-input counter and compressor circuits. IEEE Symposium on Computer Arithmetic Mayur Mehta, Vijay Parmar, Earl E. Swartzlander Jr.
1991	—	`conf`	The case for application specific computing. ASAP Earl E. Swartzlander Jr.
1991	C	`conf`	The redundant cell adder. IEEE Symposium on Computer Arithmetic Thomas W. Lynch, Earl E. Swartzlander Jr.
1990	J	`jnl`	Editorial. J. VLSI Signal Process. Earl E. Swartzlander Jr.
1990	J	`jnl`	Generic signal processor implementation with VHSIC. J. VLSI Signal Process. Earl E. Swartzlander Jr.
1989	J	`jnl`	Editorial. J. VLSI Signal Process. Earl E. Swartzlander Jr.
1989	J	`jnl`	Editorial. J. VLSI Signal Process. Earl E. Swartzlander Jr.
1989	J	`jnl`	Editorial. J. VLSI Signal Process. Earl E. Swartzlander Jr.
1985	C	`conf`	Arithmetic for high speed FFT implementation. IEEE Symposium on Computer Arithmetic Earl E. Swartzlander Jr., John A. Eldon
1985	J	`jnl`	Foreword: Advances in Distributed Computing Systems. IEEE Trans. Software Eng. Stephen F. Lundstrom, Earl E. Swartzlander Jr.
1985	Misc	`conf`	Image processing address generator chip. ICASSP John A. Eldon, Zoltan Stroll, Earl E. Swartzlander Jr.
1985	—	`conf`	VLSI Testing: A Decade of Experience. COMPCON Earl E. Swartzlander Jr., John A. Eldon, De D. Hsu
1984	Misc	`conf`	Fast transform processor implementation. ICASSP Earl E. Swartzlander Jr., George Hallnor
1983	Misc	`conf`	Digital signal processing with VLSI technology. ICASSP Earl E. Swartzlander Jr., Louis S. Lome, George Hallnor
1983	J	`jnl`	Sign/Logarithm Arithmetic for FFT Implementation. IEEE Trans. Computers Earl E. Swartzlander Jr., D. V. Satish Chandra, H. Troy Nagle Jr., Scott A. Starks
1982	J	`jnl`	Supersystems: Technology and Architecture. IEEE Trans. Computers Earl E. Swartzlander Jr., Barry K. Gilbert
1980	J	`jnl`	Arithmetic for Ultra-High-Speed Tomography. IEEE Trans. Computers Earl E. Swartzlander Jr., Barry K. Gilbert
1980	J	`jnl`	Merged Arithmetic. IEEE Trans. Computers Earl E. Swartzlander Jr.
1980	Misc	`conf`	Signal processing architectures with VLSI. ICASSP Earl E. Swartzlander Jr.
1979	J	`jnl`	A Routing Algorithm for Signal Processing Networks. IEEE Trans. Computers Earl E. Swartzlander Jr., Douglas J. Heath
1979	J	`jnl`	Comment on "The Focus Number System". IEEE Trans. Computers Earl E. Swartzlander Jr.
1979	J	`jnl`	Microprogrammed Control for Specialized Processors. IEEE Trans. Computers Earl E. Swartzlander Jr.
1978	J	`jnl`	Inner Product Computers. IEEE Trans. Computers Earl E. Swartzlander Jr., Barry K. Gilbert, Irving S. Reed
1978	C	`conf`	Merged arithmetic for signal processing. IEEE Symposium on Computer Arithmetic Earl E. Swartzlander Jr.
1977	A*	`conf`	Microprogrammed control for signal processing. MICRO Earl E. Swartzlander Jr.
1975	J	`jnl`	The Sign/Logarithm Number System. IEEE Trans. Computers Earl E. Swartzlander Jr., Aristides G. Alexopoulos
1973	—	`conf`	Applications of the inner product computer. ACM Annual Conference Earl E. Swartzlander Jr.
1973	J	`jnl`	Parallel Counters. IEEE Trans. Computers Earl E. Swartzlander Jr.
1973	J	`jnl`	Review of "Fundamentals of Pattern Recognition" by Edward A. Patrick. IEEE Trans. Syst. Man Cybern. Earl E. Swartzlander Jr.
1973	J	`jnl`	Review of "Introduction to Mathematical Techniques in Pattern Recognition" by Harry C. Andrews. IEEE Trans. Syst. Man Cybern. Earl E. Swartzlander Jr.
1973	J	`jnl`	The Quasi-Serial Multiplier. IEEE Trans. Computers Earl E. Swartzlander Jr.
1973	J	`jnl`	The inner product computer (Ph.D. Thesis abstr.). IEEE Trans. Inf. Theory Earl E. Swartzlander Jr.