Duy-Hieu Bui

18 papers C 1Journal 6Unranked 11
YearRankTypeTitle / Venue / Authors
2025 — conf
Exploring 0.3V Inverter Based OTA Designs with NOR3-Based Common Mode Feedback.
NewCAS
Riccardo Della Sala, Orazio Aiello, Ngo-Doanh Nguyen, Duy-Hieu Bui, Xuan-Tu Tran, Giuseppe Scotti
2025 — conf
LogicCraft: LLM-Assisted Optimization of Netlist to Layout for Complex Custom Standard Cell Designs.
AICAS
Minwei Lin, Duy-Hieu Bui, Chao Wang, Wangzilu Lu, Ruoyu Tang, Qing Zhang, Yuhang Zhang, Jian Zhao, Xuan-Tu Tran, Yongfu Li
2025 J jnl
SRAM-based Physically Unclonable Function using Lightweight Hamming-Code Fuzzy Extractor for Energy Harvesting Beat Sensors.
CoRR
Hoang-Long Pham, Duy-Hieu Bui, Xuan-Tu Tran, Orazio Aiello
2024 C conf
Fully Synthesizable Dynamic Voltage Comparator across technology nodes and scaled supply voltages.
ISCAS
Duy-Hieu Bui, Duc-Manh Tran, Daniele D. Caviglia, Orazio Aiello
2023 J jnl
A Hardware Architecture of NIST Lightweight Cryptography Applied in IPSec to Secure High-Throughput Low-Latency IoT Networks.
IEEE Access
Sy-Nam Tran, Van-Thuc Hoang, Duy-Hieu Bui
2023 — conf
Low-cost Low-Power Implementation of Binary Edwards Curve for Secure Passive RFID Tags.
MCSoC
Hiep Manh Dao, Vincent Beroulle, Yann Kieffer, Xuan-Tu Tran, Duy-Hieu Bui
2022 — conf
An Adaptive Hardware Architecture using Quantized HOG Features for Object Detection.
ICICDT
Ngo-Doanh Nguyen, Duy-Hieu Bui, Fawnizu Azmadi Hussin, Xuan-Tu Tran
2020 — conf
A Lightweight AEAD encryption core to secure IoT applications.
APCCAS
Ngo-Doanh Nguyen, Duy-Hieu Bui, Xuan-Tu Tran
2020 J jnl
Reducing Bitrate and Increasing the Quality of Inter Frame by Avoiding Quantization Errors in Stationary Blocks.
EAI Endorsed Trans. Ind. Networks Intell. Syst.
Xuan-Tu Tran, Ngoc-Sinh Nguyen, Duy-Hieu Bui, Minh-Trien Pham, Hung K. Nguyen, Cong-Kha Pham
2019 — conf
A Novel Hardware Architecture for Human Detection using HOG-SVM Co-Optimization.
APCCAS
Ngo-Doanh Nguyen, Duy-Hieu Bui, Xuan-Tu Tran
2019 — conf
An Efficient Event-driven Neuromorphic Architecture for Deep Spiking Neural Networks.
SoCC
Duy-Anh Nguyen, Duy-Hieu Bui, Francesca Iacopi, Xuan-Tu Tran
2017 J jnl
AES Datapath Optimization Strategies for Low-Power Low-Energy Multisecurity-Level Internet-of-Things Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Duy-Hieu Bui, Diego Puschini, Simone Bacles-Min, Edith Beigné, Xuan-Tu Tran
2017 J jnl
AXI-NoC: High-Performance Adaptation Unit for ARM Processors in Network-on-Chip Architectures.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Xuan-Tu Tran, Tung Nguyen, Hai-Phong Phan, Duy-Hieu Bui
2017 J jnl
Adaptive Architectures, Circuits and Technology Solutions for Future IoT Systems.
J. Low Power Electron.
Marc Belleville, Anca Molnos, Gilles Sicard, Jean-Frédéric Christmann, Dominique Morche, Duy-Hieu Bui, Diego Puschini, Suzanne Lesecq, Edith Beigné
2016 — conf
Ultra low-power and low-energy 32-bit datapath AES architecture for IoT applications.
ICICDT
Duy-Hieu Bui, Diego Puschini, Simone Bacles-Min, Edith Beigné, Xuan-Tu Tran
2014 — conf
H.264/AVC hardware encoders and low-power features.
APCCAS
Ngoc-Mai Nguyen, Edith Beigné, Suzanne Lesecq, Duy-Hieu Bui, Nam-Khanh Dang, Xuan-Tu Tran
2014 — conf
Reducing temporal redundancy in MJPEG using Zipfian estimation techniques.
APCCAS
Ngoc-Sinh Nguyen, Duy-Hieu Bui, Xuan-Tu Tran
2013 — conf
High-performance adaption of ARM processors into Network-on-Chip architectures.
SoCC
Tung Nguyen, Duy-Hieu Bui, Hai-Phong Phan, Trong-Trinh Dang, Xuan-Tu Tran