Dustin Richmond

26 papers A* 3A 4B 2Misc 2Journal 8Unranked 7

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	Pentimento: Data Remanence in Cloud FPGAs. ASPLOS (2) Colin Drewes, Olivia Weng, Andres Meza, Alric Althoff, David Kohlbrenner, Ryan Kastner, Dustin Richmond
2024	J	`jnl`	Scalable MatMul-free Language Modeling. CoRR Rui-Jie Zhu, Yu Zhang, Ethan Sifferman, Tyler Sheaves, Yiqiao Wang, Dustin Richmond, Peng Zhou, Jason K. Eshraghian
2024	A*	`conf`	Scalable, Programmable and Dense: The HammerBlade Open-Source RISC-V Manycore. ISCA Dai Cheol Jung, Max Ruttenberg, Paul Gao, Scott Davidson, Daniel Petrisko, Kangli Li, Aditya K. Kamath, Lin Cheng, Shaolin Xie, Peitian Pan, Zhongyuan Zhao, Zichao Yue, Bandhav Veluri, Sripathi Muralitharan, Adrian Sampson, Andrew Lumsdaine, Zhiru Zhang, Christopher Batten, Mark Oskin, Dustin Richmond, Michael Bedford Taylor
2024	J	`jnl`	Turn on, Tune in, and Listen up: Maximizing Side-Channel Recovery in Cross-Platform Time-to-Digital Converters. ACM Trans. Reconfigurable Technol. Syst. Colin Drewes, Tyler Sheaves, Olivia Weng, Keegan Ryan, Bill Hunter, Christopher McCarty, Ryan Kastner, Dustin Richmond
2023	—	`conf`	Beyond Static Parallel Loops: Supporting Dynamic Task Parallelism on Manycore Architectures with Software-Managed Scratchpad Memories. ASPLOS (3) Lin Cheng, Max Ruttenberg, Dai Cheol Jung, Dustin Richmond, Michael B. Taylor, Mark Oskin, Christopher Batten
2023	J	`jnl`	Pentimento: Data Remanence in Cloud FPGAs. CoRR Colin Drewes, Olivia Weng, Andres Meza, Alric Althoff, David Kohlbrenner, Ryan Kastner, Dustin Richmond
2023	A	`conf`	Turn on, Tune in, Listen up: Maximizing Side-Channel Recovery in Time-to-Digital Converters. FPGA Colin Drewes, Olivia Weng, Keegan Ryan, Bill Hunter, Christopher McCarty, Ryan Kastner, Dustin Richmond
2022	J	`jnl`	A Tensor Processing Framework for CPU-Manycore Heterogeneous Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lin Cheng, Peitian Pan, Zhongyuan Zhao, Krithik Ranjan, Jack Weber, Bandhav Veluri, Seyed Borna Ehsani, Max Ruttenberg, Dai Cheol Jung, Preslav Ivanov, Dustin Richmond, Michael B. Taylor, Zhiru Zhang, Christopher Batten
2021	Misc	`conf`	A Tunable Dual-Edge Time-to-Digital Converter. FCCM Colin Drewes, Steven Harris, Winnie Wang, Richard Appen, Olivia Weng, Ryan Kastner, William Hunter, Christopher McCarty, Dustin Richmond
2021	A*	`conf`	Classifying Computations on Multi-Tenant FPGAs. DAC Mustafa S. Gobulukoglu, Colin Drewes, William Hunter, Ryan Kastner, Dustin Richmond
2021	A	`conf`	Classifying Computations on Multi-Tenant FPGAs. FPGA Mustafa S. Gobulukoglu, Colin Drewes, Bill Hunter, Dustin Richmond, Ryan Kastner
2021	A*	`conf`	Taming the Zoo: The Unified GraphIt Compiler Framework for Novel Architectures. ISCA Ajay Brahmakshatriya, Emily Furst, Victor A. Ying, Claire Hsu, Changwan Hong, Max Ruttenberg, Yunming Zhang, Dai Cheol Jung, Dustin Richmond, Michael B. Taylor, Julian Shun, Mark Oskin, Daniel Sánchez, Saman P. Amarasinghe
2020	J	`jnl`	ASIC clouds: specializing the datacenter for planet-scale applications. Commun. ACM Michael Bedford Taylor, Luis Vega, Moein Khazraee, Ikuo Magaki, Scott Davidson, Dustin Richmond
2020	—	`conf`	NoC Symbiosis : (Special Session Paper). NOCS Daniel Petrisko, Chun Zhao, Scott Davidson, Paul Gao, Dustin Richmond, Michael Bedford Taylor
2020	—	`conf`	Ruche Networks: Wire-Maximal, No-Fuss NoCs : Special Session Paper. NOCS Dai Cheol Jung, Scott Davidson, Chun Zhao, Dustin Richmond, Michael Bedford Taylor
2019	—	`conf`	A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS. VLSI Circuits Austin Rovinski, Chun Zhao, Khalid Al-Hawaj, Paul Gao, Shaolin Xie, Christopher Torng, Scott Davidson, Aporva Amarnath, Luis Vega, Bandhav Veluri, Anuj Rao, Tutu Ajayi, Julian Puscar, Steve Dai, Ritchie Zhao, Dustin Richmond, Zhiru Zhang, Ian Galton, Christopher Batten, Michael B. Taylor, Ronald G. Dreslinski
2018	B	`conf`	Everyone's a Critic: A Tool for Exploring RISC-V Projects. FPL Dustin Richmond, Michael Barrow, Ryan Kastner
2018	—	`conf`	PynqCopter - An Open-source FPGA Overlay for UAVs. IEEE BigData Brennan Cain, Zain Merchant, Indira Avendano, Dustin Richmond, Ryan Kastner
2018	J	`jnl`	Synthesizable Higher-Order Functions for C++. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dustin Richmond, Alric Althoff, Ryan Kastner
2017	A	`conf`	A streaming clustering approach using a heterogeneous system for big data analysis. ICCAD Dajung Lee, Alric Althoff, Dustin Richmond, Ryan Kastner
2016	A	`conf`	Resolve: Generation of High-Performance Sorting Architectures from High-Level Synthesis. FPGA Janarbek Matai, Dustin Richmond, Dajung Lee, Zac Blair, Qiongzhi Wu, Amin Abazari, Ryan Kastner
2016	Misc	`conf`	Tinker: Generating Custom Memory Architectures for Altera's OpenCL Compiler. FCCM Dustin Richmond, Jeremy Blackstone, Matthew Hogains, Kevin Thai, Ryan Kastner
2015	J	`jnl`	RIFFA 2.1: A Reusable Integration Framework for FPGA Accelerators. ACM Trans. Reconfigurable Technol. Syst. Matthew Jacobsen, Dustin Richmond, Matthew Hogains, Ryan Kastner
2014	J	`jnl`	Enabling FPGAs for the Masses. CoRR Janarbek Matai, Dustin Richmond, Dajung Lee, Ryan Kastner
2014	—	`conf`	Real-time 3D reconstruction for FPGAs: A case study for evaluating the performance, area, and programmability trade-offs of the Altera OpenCL SDK. FPT Quentin Gautier, Alexandria Shearer, Janarbek Matai, Dustin Richmond, Pingfan Meng, Ryan Kastner
2013	B	`conf`	A FPGA design for high speed feature extraction from a compressed measurement stream. FPL Dustin Richmond, Ryan Kastner, Ali Irturk, John McGarry