Dustin Dunwell

11 papers C 3Journal 4Unranked 4
YearRankTypeTitle / Venue / Authors
2025 J jnl
Co-Design of Interchiplet, Package, and System Interconnect Protocols.
IEEE Micro
Tony Chan Carusone, Dustin Dunwell, Sundeep Gupta, Letizia Giuliano, Adrien Auge, Michael Klempa, Sue Hung Fung
2019 — conf
A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS.
ISSCC
Shayan Shahramian, Behzad Dehlaghi, Joshua Liang, Ryan Bespalko, Dustin Dunwell, James Bailey, Bo Wang, Alireza Sharif Bakhtiar, Michael O'Farrell, Kerry Tang, Anthony Chan Carusone, David Cassan, Davide Tonietto
2017 J jnl
All-Digital Calibration of Timing Mismatch Error in Time-Interleaved Analog-to-Digital Converters.
IEEE Trans. Very Large Scale Integr. Syst.
Shuai Chen, Luke Wang, Hong Zhang, Rosanah Murugesu, Dustin Dunwell, Anthony Chan Carusone
2014 C conf
A passive resonant clocking network for distribution of a 2.5-GHz clock in a flash ADC.
ISCAS
Mike Bichan, Dustin Dunwell, QiWei Wang, Anthony Chan Carusone
2013 C conf
Channel characterization using jitter measurements.
ISCAS
Dustin Dunwell, Atul Gupta, Anthony Chan Carusone
2013 J jnl
Modeling Oscillator Injection Locking Using the Phase Domain Response.
IEEE Trans. Circuits Syst. I Regul. Pap.
Dustin Dunwell, Anthony Chan Carusone
2012 — conf
A 2.3-4GHz injection-locked clock multiplier with 55.7% lock range and 10-ns power-on.
CICC
Dustin Dunwell, Anthony Chan Carusone, Jared Zerbe, Brian S. Leibowitz, Barry Daly, John C. Eble
2010 C conf
A 15-Gb/s preamplifier with 10-dB gain control and 8-mV sensitivity in 65-nm CMOS.
ISCAS
Dustin Dunwell, Anthony Chan Carusone
2010 — conf
Gain and equalization adaptation to optimize the vertical eye opening in a wireline receiver.
CICC
Dustin Dunwell, Anthony Chan Carusone
2007 J jnl
Computer design of super-orthogonal space-time trellis codes.
IEEE Trans. Wirel. Commun.
Michael Bale, Brady Laska, Dustin Dunwell, François Chan, Hamid Jafarkhani
2006 — conf
24 GHz Low-Noise Amplifiers using High Q Series-Stub Transmission Lines in 0.18µm CMOS.
CCECE
Dustin Dunwell, Brian Frank