Duo Sheng

31 papers C 1Journal 20Unranked 10
YearRankTypeTitle / Venue / Authors
2025 — conf
An All-Digital Capacitance-to-Digital Converter Based on Time-to-Digital Converter.
ICEIC
Duo Sheng, Chao-Kai Pai, Yi-Ju Chen, Bo-An Chen, Hao-Yuan Cheng, Ke-Jhong Tan, Ri-En Yeh
2024 J jnl
Low-Jitter Frequency Doubling Circuit Supporting Higher-Speed BISG and Aging Sensing in a Chiplet-Based Design Environment.
IEEE Trans. Very Large Scale Integr. Syst.
Ko-Hong Lin, Ont-Derh Lin, Shi-Yu Huang, Duo Sheng
2023 — conf
A Digital Receive Beamforming IC for High-Frequency Ultrasound Imaging System.
ASICON
Duo Sheng, Ying-Chi Chiu, Yun-Quan Li, You-Ning Lo, Chao-Kai Pai, Ten-Ling Wang
2021 — conf
DLL-Based Transmit Beamforming IC for High -Frequency Ultrasound Medical Imaging System.
ICCE-TW
Duo Sheng, Chih-Hao Liu, Sih-Ying Chen, Bin-Yang Song, Ying-Chi Chiu, Ming-Han Cai
2021 J jnl
Digitally Controlled Oscillator with High Timing Resolution and Low Complexity for Clock Generation.
Sensors
Duo Sheng, Wei-Yen Chen, Hao-Ting Huang, Li Tai
2020 J jnl
Design of a human body channel communication transceiver using convolutional codes.
Microelectron. J.
Ching-Che Chung, Duo Sheng, Ming-Hsuan Li
2020 J jnl
High-Resolution All-Digital Transmit Beamformer for High-Frequency and Wearable Ultrasound Imaging Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Duo Sheng, Jun-Wei Lin, Yi-Hsiang Wang, Chih-Chung Huang
2020 — conf
High-Timing-Resolution and Low-Complexity Cell-Based Digitally Controlled Oscillator.
ICCE-TW
Duo Sheng, Wei-Yen Chen, Yu-Hsiang Chang, Hao-Ting Huang
2019 J jnl
A fast phase tracking reference-less all-digital CDR circuit for human body channel communication.
Microelectron. J.
Ching-Che Chung, Duo Sheng, Ming-Chieh Li, Yi-Che Tsai
2016 J jnl
A Low-Power All-Digital on-Chip CMOS Oscillator for a Wireless Sensor Node.
Sensors
Duo Sheng, Min-Rong Hong
2015 J jnl
A High Resolution On-Chip Delay Sensor with Low Supply-Voltage Sensitivity for High-Performance Electronic Systems.
Sensors
Duo Sheng, Hsiu-Fan Lai, Sheng-Min Chan, Min-Rong Hong
2015 J jnl
A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator.
IEEE Trans. Very Large Scale Integr. Syst.
Ching-Che Chung, Duo Sheng, Wei-Da Ho
2015 J jnl
A Wide-Range Low-Cost All-Digital Duty-Cycle Corrector.
IEEE Trans. Very Large Scale Integr. Syst.
Ching-Che Chung, Duo Sheng, Chang-Jun Li
2014 — conf
An all-digital phase-locked loop compiler with liberty timing files.
VLSI-DAT
Ching-Che Chung, Duo Sheng, Chen-Han Chen
2014 J jnl
High-Resolution All-Digital Duty-Cycle Corrector in 65-nm CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst.
Ching-Che Chung, Duo Sheng, Sung-En Shen
2014 J jnl
High-resolution and all-digital on-chip delay measurement with low supply sensitivity for SoC applications.
IEICE Electron. Express
Duo Sheng, Ching-Che Chung, Hsiu-Fan Lai, Shu-Syun Jhao
2013 — conf
A 0.5V/1.0V fast lock-in ADPLL for DVFS battery-powered devices.
VLSI-DAT
Ching-Che Chung, Duo Sheng, Wei-Siang Su
2013 J jnl
A counter-based all-digital spread-spectrum clock generator with high EMI reduction in 65nm CMOS.
IEICE Electron. Express
Ching-Che Chung, Duo Sheng, Wei-Da Ho
2013 — conf
A high-resolution and one-cycle conversion time-to-digital converter architecture for PET image applications.
EMBC
Duo Sheng, Ching-Che Chung, Chih-Chung Huang, Jia-Wei Jian
2012 J jnl
A high-performance wear-leveling algorithm for flash memory system.
IEICE Electron. Express
Ching-Che Chung, Duo Sheng, Ning-Mi Hsueh
2012 — conf
A low-power and small-area all-digital spread-spectrum clock generator in 65nm CMOS technology.
VLSI-DAT
Ching-Che Chung, Duo Sheng, Wei-Da Ho
2012 J jnl
An All-Digital Large-N Audio Frequency Synthesizer for HDMI Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Ching-Che Chung, Duo Sheng, Chia-Lin Chang, Wei-Da Ho, Yang-Di Lin, Fang-Nien Lu
2011 J jnl
A 600kHz to 1.2GHz all-digital delay-locked loop in 65nm CMOS technology.
IEICE Electron. Express
Ching-Che Chung, Duo Sheng, Chia-Lin Chang
2011 J jnl
A Low-Power and Portable Spread Spectrum Clock Generator for SoC Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Duo Sheng, Ching-Che Chung, Chen-Yi Lee
2011 J jnl
A wide-range all-digital duty-cycle corrector with output clock phase alignment in 65nm CMOS technology.
IEICE Electron. Express
Ching-Che Chung, Duo Sheng, Sung-En Shen
2010 J jnl
Fast-lock all-digital DLL and digitally-controlled phase shifter for DDR controller applications.
IEICE Electron. Express
Duo Sheng, Ching-Che Chung, Chen-Yi Lee
2008 — conf
An all digital spread spectrum clock generator with programmable spread ratio for SoC applications.
APCCAS
Duo Sheng, Ching-Che Chung, Chen-Yi Lee
2007 J jnl
An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Duo Sheng, Ching-Che Chung, Chen-Yi Lee
2006 — conf
A Fast-Lock-In ADPLL with High-Resolution and Low-Power DCO for SoC Applications.
APCCAS
Duo Sheng, Ching-Che Chung, Chen-Yi Lee
2000 C conf
A compact adaptive equalizer IC for HIPERLAN system.
ISCAS
Jinn-Shyan Wang, Pei-Lung Lin, Wern-Ho Sheen, Duo Sheng, Yu-Ming Huang
2000 J jnl
Design of a 3-V 300-MHz low-power 8-b×8-b pipelined multiplier using pulse-triggered TSPC flip-flops.
IEEE J. Solid State Circuits
Jinn-Shyan Wang, Po-Hui Yang, Duo Sheng