Dunshan Yu

57 papers A* 1B 1C 8Journal 27Unranked 20
YearRankTypeTitle / Venue / Authors
2026 — conf
8.4 A 112Gb/S/Wire Single-Ended Simultaneous Bi-Directional Transceiver with Dynamic Equalizer for Die-to-Die Interface in 28nm CMOS.
ISSCC
Zhiwen Huang, Zhifei Wang, Bingyi Ye, Tianchen Ye, Dunshan Yu, Wei Wang, Weixin Gai
2025 — conf
25.5 A 99.5mW/Port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS.
ISSCC
Guangdong Wu, Yuanliang Li, Bingyi Ye, Fangzhu Li, Xin Liu, Haowei Niu, Ruixu Wang, Dunshan Yu, Weixin Gai
2025 — conf
A 1.11pJ/b 224Gb/s XSR Receiver with Slice-Based CTLE and PI-Based Clock Generator in 12nm CMOS.
ISSCC
Bingyi Ye, Tianchen Ye, Tianyuan Zhong, Zhiwen Huang, Lei Shen, Boyang Zhang, Dunshan Yu, Yandong He, Weixin Gai
2025 — conf
A 64Gb/s/wire 10.5Tb/s/mm/Layer Single-Ended Simultaneous Bi-Directional Transceiver with Echo and Crosstalk Cancellation for a Die-to-Die Interface in 28nm CMOS.
ISSCC
Zhifei Wang, Zhiwen Huang, Tianchen Ye, Bingyi Ye, Fangzhu Li, Wei Wang, Dunshan Yu, Weixin Gai
2025 C conf
A Compact Full Pipeline Architecture of SM3 Algorithm with High throughput and High Efficiency.
ISCAS
Tuo Li, Chao Cheng, Changhong Wang, Ruiting Wang, Xiaofeng Zou, Dunshan Yu
2025 A* conf
Towards Effective and Sparse Adversarial Attack on Spiking Neural Networks via Breaking Invisible Surrogate Gradients.
CVPR
Li Lun, Kunyu Feng, Qinglong Ni, Ling Liang, Yuan Wang, Ying Li, Dunshan Yu, Xiaoxin Cui
2025 J jnl
Towards Effective and Sparse Adversarial Attack on Spiking Neural Networks via Breaking Invisible Surrogate Gradients.
CoRR
Li Lun, Kunyu Feng, Qinglong Ni, Ling Liang, Yuan Wang, Ying Li, Dunshan Yu, Xiaoxin Cui
2024 — conf
An Efficient Spiking Convolutional Architecture with Compressed Address Event Representation and Adaptive Delay Asynchronous Clocks.
BioCAS
Zhenhui Dai, Li Lun, Zilin Wang, Jiawei Wang, Kunyu Feng, Yuan Wang, Dunshan Yu, Xiaoxin Cui
2024 C conf
An Energy-Efficient Differential Frame Convolutional Accelerator with on-Chip Fusion Storage Architecture and Pixel-Level Pipeline Data Flow.
ISCAS
Zhenhui Dai, Jiawei Wang, Yi Zhong, Kunyu Feng, Cheng Zhao, Yuanyuan Jiang, Peiyu Chen, Yuan Wang, Dunshan Yu, Xiaoxin Cui
2023 J jnl
A multichannel readout integrated circuit with column-wise pseudo differential extended counting ADCs for an uncooled infrared focal plane array based on silicon diodes.
Microelectron. J.
Ye Zhou, Wengao Lu, Shanzhe Yu, Dunshan Yu, Yacong Zhang, Zhongjian Chen
2023 J jnl
Multimodal Affective States Recognition Based on Multiscale CNNs and Biologically Inspired Decision Fusion Model.
IEEE Trans. Affect. Comput.
Yuxuan Zhao, Xinyan Cao, Jinlong Lin, Dunshan Yu, Xixin Cao
2022 C conf
An Event-driven Spiking Neural Network Accelerator with On-chip Sparse Weight.
ISCAS
Yisong Kuang, Xiaoxin Cui, Chenglong Zou, Yi Zhong, Zhenhui Dai, Zilin Wang, Kefei Liu, Dunshan Yu, Yuan Wang
2022 J jnl
ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator.
IEEE Trans. Very Large Scale Integr. Syst.
Yisong Kuang, Xiaoxin Cui, Zilin Wang, Chenglong Zou, Yi Zhong, Kefei Liu, Zhenhui Dai, Dunshan Yu, Yuan Wang, Ru Huang
2021 C conf
A 28-nm 0.34-pJ/SOP Spike-Based Neuromorphic Processor for Efficient Artificial Neural Network Implementations.
ISCAS
Yisong Kuang, Xiaoxin Cui, Yi Zhong, Kefei Liu, Chenglong Zou, Zhenhui Dai, Dunshan Yu, Yuan Wang, Ru Huang
2021 J jnl
A 64K-Neuron 64M-1b-Synapse 2.64pJ/SOP Neuromorphic Chip With All Memory on Chip for Spike-Based Models in 65nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Yisong Kuang, Xiaoxin Cui, Yi Zhong, Kefei Liu, Chenglong Zou, Zhenhui Dai, Yuan Wang, Dunshan Yu, Ru Huang
2021 — conf
A Novel Circuit Authentication Scheme Based on Partial Polymorphic Gates.
AsianHOST
Timothy Dunlap, Omid Aramoon, Gang Qu, Tian Wang, Xiaoxin Cui, Dunshan Yu
2021 — conf
Low Power Readout Integrated Circuit with PFM-based ADCs Employing Residue Quantization for Uncooled Infrared Imagers.
ASICON
Ye Zhou, Shanzhe Yu, Wengao Lu, Dunshan Yu, Yacong Zhang, Zhongjian Chen
2020 B conf
A 3D Convolutional Neural Network for Emotion Recognition based on EEG Signals.
IJCNN
Yuxuan Zhao, Jin Yang, Jinlong Lin, Dunshan Yu, Xixin Cao
2020 J jnl
Fully on-chip clock jitter and skew measurement scheme via incoherent subsampling.
Microelectron. J.
Yinxuan Lyu, Jianhua Feng, Kai Zhu, Hongfei Ye, Dunshan Yu
2019 J jnl
A New Method for Futures Price Trends Forecasting Based on BPNN and Structuring Data.
IEICE Trans. Inf. Syst.
Weijun Lu, Chao Geng, Dunshan Yu
2019 — conf
Designing a 3D Graphics Processor for Mobile Applications.
ASICON
Lingjuan Wu, Wenqian Zhao, Dunshan Yu
2019 — conf
FPGA Implementation of Quantized Convolutional Neural Networks.
ICCT
Qi Zhang, Jian Cao, Ying Zhang, Shiguang Zhang, Quan Zhang, Dunshan Yu
2019 — conf
Improved Discrete Wavelet Analysis and Principal Component Analysis for EEG Signal Processing.
ASICON
Yi-Hsiang Chen, Xiaoxin Cui, Kanglin Xiao, Dunshan Yu
2019 J jnl
Multimodal Emotion Recognition Model using Physiological Signals.
CoRR
Yuxuan Zhao, Xinyan Cao, Jinlong Lin, Dunshan Yu, Xixin Cao
2019 — conf
Perceptual Fast CU Size Decision Algorithm for AVS2 Intra Coding.
BigMM
Hao Xie, Guoqing Xiang, Dunshan Yu, Hong Yu, Yuan Li, Wei Yan
2018 C conf
A 108fs
ISCAS
Yinxuan Lyu, Jianhua Feng, Chenfeng Tu, Linqi Shi, Hongfei Ye, Weixin Gai, Dunshan Yu
2018 — conf
A Novel Polymorphic Gate Based Circuit Fingerprinting Technique.
ACM Great Lakes Symposium on VLSI
Tian Wang, Xiaoxin Cui, Dunshan Yu, Omid Aramoon, Timothy Dunlap, Gang Qu, Xiaole Cui
2018 J jnl
Design of Low-Power High-Performance FinFET Standard Cells.
Circuits Syst. Signal Process.
Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Dunshan Yu, Xiaole Cui
2018 J jnl
Evaluation of Dynamic-Adjusting Threshold-Voltage Scheme for Low-Power FinFET Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Tian Wang, Xiaoxin Cui, Yewen Ni, Dunshan Yu, Xiaole Cui
2018 — conf
Polymorphic gate based IC watermarking techniques.
ASP-DAC
Tian Wang, Xiaoxin Cui, Dunshan Yu, Omid Aramoon, Timothy Dunlap, Gang Qu, Xiaole Cui
2017 — conf
A practical cold boot attack on RSA private keys.
AsianHOST
Tian Wang, Xiaoxin Cui, Yewen Ni, Dunshan Yu, Xiaole Cui, Gang Qu
2017 J jnl
High-Performance Noninvasive Side-Channel Attack Resistant ECC Coprocessor for GF(2m ).
IEEE Trans. Ind. Electron.
Kai Liao, Xiaoxin Cui, Nan Liao, Tian Wang, Dunshan Yu, Xiaole Cui
2017 J jnl
Improving DFA attacks on AES with unknown and random faults.
Sci. China Inf. Sci.
Nan Liao, Xiaoxin Cui, Kai Liao, Tian Wang, Dunshan Yu, Xiaole Cui
2016 J jnl
Efficient Weak Signals Acquisition Strategy for GNSS Receivers.
IEICE Trans. Commun.
Weijun Lu, Yanbin Zhang, Dengyun Lei, Dunshan Yu
2016 J jnl
Improving tracking accuracy with subcarrier assistance and code monitoring for BOC modulated signal.
Comput. Electr. Eng.
Yanbin Zhang, Weijun Lu, Ruiyuan Liu, Dunshan Yu
2016 J jnl
Low Power High Performance FinFET Standard Cells Based on Mixed Back Biasing Technology.
IEICE Trans. Electron.
Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Xiaole Cui, Dunshan Yu
2016 J jnl
Ultralow-power high-speed flip-flop based on multimode FinFETs.
Sci. China Inf. Sci.
Kai Liao, Xiaoxin Cui, Nan Liao, Tian Wang, Dunshan Yu, Xiaole Cui
2015 — conf
A high-efficient and accurate fault model aiming at FPGA-based AES cryptographic applications.
ASICON
Nan Liao, Xiaoxin Cui, Tian Wang, Kai Liao, Yewen Ni, Dunshan Yu, Xiaole Cui
2015 J jnl
Balance Differential Coherent Bit Synchronization Algorithm for GNSS Receiver.
IEICE Trans. Commun.
Dengyun Lei, Weijun Lu, Yanbin Zhang, Dunshan Yu
2015 — conf
Employing the mixed FBB/RBB in the design of FinFET logic gates.
ASICON
Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Yewen Ni, Dunshan Yu, Xiaole Cui
2015 J jnl
Key characterization factors of accurate power modeling for FinFET circuits.
Sci. China Inf. Sci.
Kaisheng Ma, Xiaoxin Cui, Kai Liao, Nan Liao, Di Wu, Dunshan Yu
2014 J jnl
Effective PPS Signal Generation with Predictive Synchronous Loop for GPS.
IEICE Trans. Commun.
Yanbin Zhang, Weijun Lu, Dengyun Lei, Yongcan Huang, Dunshan Yu
2014 C conf
High-speed constant-time division module for Elliptic Curve Cryptography based on GF(2
ISCAS
Kai Liao, Xiaoxin Cui, Nan Liao, Tian Wang, Xiao Zhang, Ying Huang, Dunshan Yu
2014 J jnl
Low power adiabatic logic based on FinFETs.
Sci. China Inf. Sci.
Nan Liao, Xiaoxin Cui, Kai Liao, Kaisheng Ma, Di Wu, Wei Wei, Rui Li, Dunshan Yu
2014 J jnl
Resource-efficient acquisition architecture for BOC-modulated signals.
IEICE Electron. Express
Dengyun Lei, Weijun Lu, Dunshan Yu
2014 J jnl
Ultra-low power dissipation of improved complementary pass-transistor adiabatic logic circuits based on FinFETs.
Sci. China Inf. Sci.
Kai Liao, Xiaoxin Cui, Nan Liao, Kaisheng Ma, Di Wu, Wei Wei, Rui Li, Dunshan Yu
2013 C conf
A Dynamic-Adjusting Threshold-Voltage Scheme for FinFETs low power designs.
ISCAS
Xiaoxin Cui, Kaisheng Ma, Kai Liao, Nan Liao, Di Wu, Wei Wei, Rui Li, Dunshan Yu
2013 J jnl
A Low-noise High-voltage Interface Circuit for capacitive MEMS gyroscope.
J. Circuits Syst. Comput.
Ran Fang, Wengao Lu, Guannan Wang, Tingting Tao, Yacong Zhang, Zhongjian Chen, Dunshan Yu
2013 J jnl
A capacitive Interface Circuit with capacitor mismatch Auto-compensation for MEMS gyroscope.
J. Circuits Syst. Comput.
Ran Fang, Wengao Lu, Guannan Wang, Tingting Tao, Yacong Zhang, Zhongjian Chen, Dunshan Yu
2013 J jnl
Design of a Reconfigurable Acoustic Modem for Underwater Sensor Networks.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Lingjuan Wu, Ryan Kastner, Bo Gu, Dunshan Yu
2011 — conf
A JTAG-based configuration circuit applied in SerDes chip.
ASICON
Xun Jiang, Xiaoxin Cui, Dunshan Yu
2009 J jnl
A Low Cost Correlator Structure in the Pseudo-Noise Code Acquisition System.
IEICE Trans. Commun.
Weijun Lu, Ying Li, Dunshan Yu, Xing Zhang
2009 J jnl
Application-Dependent Interconnect Testing of Xilinx FPGAs Based on Line Branches Partitioning.
IEICE Trans. Inf. Syst.
Teng Lin, Jianhua Feng, Dunshan Yu
2006 — conf
A CMOS Differential Difference Amplifier with Reduced Nonlinearity Error of Interpolation for Interpolating ADCs.
APCCAS
Xin Zhang, Dunshan Yu, Shimin Sheng
2006 — conf
A Discrete STFT Processor for Real-time Spectrum Analysis.
APCCAS
Shiqun Zhang, Dunshan Yu, Shimin Sheng
2006 C conf
An Efficient VLSI Implementation of Distributed Architecture for DWT.
MMSP
Xixin Cao, Qingqing Xie, Chungan Peng, Qingchun Wang, Dunshan Yu
2006 — conf
Design and Implementation of a 2-level FSK Digital Modems Using CORDIC Algorithm.
APCCAS
Xiaoxin Cui, Dunshan Yu, Shimin Sheng, Xiaole Cui