Duncan M. Hank Walker

12 papers A 1B 1Misc 3Journal 5Unranked 1
YearRankTypeTitle / Venue / Authors
2023 J jnl
Topological Heuristics for Scan Test Overhead Reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Avijit Chakraborty, Duncan M. Hank Walker
2015 — conf
At-Speed Path Delay Test.
NATW
Swati Chakraborty, Duncan M. Hank Walker
2014 Misc conf
Improved power supply noise control for pseudo functional test.
VTS
Tengteng Zhang, Duncan M. Hank Walker
2014 — ch.
K Longest Paths.
Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits
Duncan M. Hank Walker
2013 Misc conf
Power supply noise control in pseudo functional test.
VTS
Tengteng Zhang, Duncan M. Hank Walker
2009 Misc conf
Compact Delay Test Generation with a Realistic Low Cost Fault Coverage Metric.
VTS
Zheng Wang, Duncan M. Hank Walker
2007 J jnl
Modeling Power Supply Noise in Delay Testing.
IEEE Des. Test Comput.
Jing Wang, Duncan M. Hank Walker, Xiang Lu, Ananta K. Majhi, Bram Kruseman, Guido Gronthoud, Luis Elvira Villagra, Paul J. A. M. van de Wiel, Stefan Eichenberger
2005 J jnl
IC Outlier Identification Using Multiple Test Metrics.
IEEE Des. Test Comput.
Sagar S. Sabade, Duncan M. Hank Walker
2005 B conf
Reliable energy efficient routing in wireless sensor networks.
MASS
Eunjae Jung, Duncan M. Hank Walker
1994 J jnl
Semiconductor wafer representation for TCAD.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Martin D. Giles, Duane S. Boning, Goodwin R. Chin, Walter C. Dietrich Jr., Michael S. Karasick, Mark E. Law, Purnendu K. Mozumder, Lee R. Nackman, V. T. Rajan, Duncan M. Hank Walker, Robert H. Wang, Alexander S. Wong
1993 A conf
Test quality and yield analysis using the DEFAM defect to fault mapper.
ICCAD
Dinesh D. Gaitonde, Duncan M. Hank Walker
1990 J jnl
DVLASIC: catastrophic fault yield simulation in a distributed processing environment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Duncan M. Hank Walker, D. S. Nydick