Duckgyu Shin - RankMe

15 papers Journal 11Unranked 4

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Energy-Efficient p-Bit-Based Fully-Connected Quantum-Inspired Simulated Annealer with Dual BRAM Architecture. CoRR Naoya Onizawa, Taiga Kubuta, Duckgyu Shin, Takahiro Hanyu
2026	J	`jnl`	Energy-Efficient p-bit-Based Fully-Connected Quantum-Inspired Simulated Annealer With Dual BRAM Architecture. IEEE Access Naoya Onizawa, Taiga Kubuta, Duckgyu Shin, Takahiro Hanyu
2026	J	`jnl`	Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing. CoRR Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu
2024	J	`jnl`	Stochastic Simulated Quantum Annealing for Fast Solution of Combinatorial Optimization Problems. IEEE Access Naoya Onizawa, Ryoma Sasaki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu
2023	J	`jnl`	Fast-Converging Simulated Annealing for Ising Models Based on Integral Stochastic Computing. IEEE Trans. Neural Networks Learn. Syst. Naoya Onizawa, Kota Katsuki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu
2023	—	`conf`	Improving Stochastic Quantum-Like Annealing Based on Rerandomization. ICECS Ryoma Sasaki, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu
2023	J	`jnl`	Local Energy Distribution Based Hyperparameter Determination for Stochastic Simulated Annealing. CoRR Naoya Onizawa, Kyo Kuroki, Duckgyu Shin, Takahiro Hanyu
2023	J	`jnl`	Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing. IEEE J. Emerg. Sel. Topics Circuits Syst. Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu
2023	—	`conf`	Stochastic Implementation of Simulated Quantum Annealing on PYNQ. ICFPT Taiga Kubuta, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu
2023	J	`jnl`	Stochastic Quantum Monte Carlo Algorithm for Large-Scale Combinatorial Optimization Problems. CoRR Naoya Onizawa, Ryoma Sasaki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu
2022	—	`conf`	Fast Solving Complete 2000-Node Optimization Using Stochastic-Computing Simulated Annealing. ICECS 2022 Kota Katsuki, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu
2022	J	`jnl`	Implementation of CMOS Invertible Logic on Zynq-SoC Platform: A Case Study of Training BNN. FLAP Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu
2020	J	`jnl`	Fast Hardware-based Learning Algorithm for Binarized Perceptrons using CMOS Invertible Logic. FLAP Naoya Onizawa, Duckgyu Shin, Takahiro Hanyu
2020	J	`jnl`	Training Hardware for Binarized Convolutional Neural Network Based on CMOS Invertible Logic. IEEE Access Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu
2019	—	`conf`	FPGA Implementation of Binarized Perceptron Learning Hardware Using CMOS Invertible Logic. ICECS Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu