Douglas L. Maskell

125 papers A 9B 10C 10Misc 7Journal 55Unranked 34

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Portfolio Rebalancing using Deep Reinforcement Learning. ICCAI Trakal Kum, Ethan Koay, Douglas L. Maskell, Chai Quek
2024	—	`conf`	A New Carry Look-Ahead Adder Architecture Enabling Improved Speed and Energy Efficiency. PACRIM Padmanabhan Balasubramanian, Douglas L. Maskell
2024	J	`jnl`	Fast Bipartitioned Hybrid Adder Utilizing Carry Select and Carry Lookahead Logic. CoRR Padmanabhan Balasubramanian, Douglas L. Maskell
2024	J	`jnl`	Neural Combinatorial Optimization Algorithms for Solving Vehicle Routing Problems: A Comprehensive Survey with Perspectives. CoRR Xuan Wu, Di Wang, Lijie Wen, Yubin Xiao, Chunguo Wu, Yuesong Wu, Chaoyu Yu, Douglas L. Maskell, You Zhou
2023	J	`jnl`	A Scalable Systolic Accelerator for Estimation of the Spectral Correlation Density Function and Its FPGA Implementation. ACM Trans. Reconfigurable Technol. Syst. Xiangwei Li, Douglas L. Maskell, Carol Jingyi Li, Philip H. W. Leong, David Boland
2023	J	`jnl`	Fault-Tolerant Design Approach Based on Approximate Computing. CoRR P. Balasubramanian, Douglas L. Maskell
2022	J	`jnl`	Approximator: A Software Tool for Automatic Generation of Approximate Arithmetic Circuits. Comput. Padmanabhan Balasubramanian, Raunaq Nayar, Okkar Min, Douglas L. Maskell
2022	J	`jnl`	Coarse Grained FPGA Overlay for Rapid Just-In-Time Accelerator Compilation. IEEE Trans. Parallel Distributed Syst. Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy
2021	J	`jnl`	An Approximate Adder With a Near-Normal Error Distribution: Design, Error Analysis and Practical Application. IEEE Access Padmanabhan Balasubramanian, Raunaq Nayar, Douglas L. Maskell, Nikos E. Mastorakis
2021	—	`conf`	An Approximate Adder with Reduced Error and Optimized Design Metrics. APCCAS Padmanabhan Balasubramanian, Raunaq Nayar, Douglas L. Maskell
2021	J	`jnl`	Gate-Level Static Approximate Adders. CoRR P. Balasubramanian, Raunaq Nayar, Douglas L. Maskell
2020	J	`jnl`	Area Optimized Quasi Delay Insensitive Majority Voter for TMR Applications. CoRR P. Balasubramanian, Douglas L. Maskell, Nikos E. Mastorakis
2020	A	`conf`	Energy Efficient In-memory Integer Multiplication Based on Racetrack Memory. ICDCS Tao Luo, Wei Zhang, Bingsheng He, Cheng Liu, Douglas L. Maskell
2020	—	`conf`	Hardware Optimized Approximate Adder with Normal Error Distribution. ISVLSI Raunaq Nayar, Padmanabhan Balasubramanian, Douglas L. Maskell
2020	C	`conf`	High Throughput Accelerator Interface Framework for a Linear Time-Multiplexed FPGA Overlay. ISCAS Xiangwei Li, Kizheppatt Vipin, Douglas L. Maskell, Suhaib A. Fahmy, Abhishek Kumar Jain
2019	—	`conf`	Area Optimized Quasi Delay Insensitive Majority Voter for TMR Applications. EECS P. Balasubramanian, Douglas L. Maskell, Nikos E. Mastorakis
2019	J	`jnl`	Asynchronous Early Output Block Carry Lookahead Adder with Improved Quality of Results. CoRR P. Balasubramanian, Douglas L. Maskell, Nikos E. Mastorakis
2019	J	`jnl`	Generalized Majority Voter Design Method for N-Modular Redundant Systems Used in Mission- and Safety-Critical Applications. Comput. Jaytrilok Choudhary, P. Balasubramanian, Danny M. Varghese, Dhirendra Pratap Singh, Douglas L. Maskell
2019	J	`jnl`	Indicating Asynchronous Array Multipliers. CoRR P. Balasubramanian, Douglas L. Maskell
2019	J	`jnl`	Indicating Asynchronous Multipliers. CoRR P. Balasubramanian, Douglas L. Maskell, Nikos E. Mastorakis
2019	J	`jnl`	Majority and Minority Voted Redundancy for Safety-Critical Applications. CoRR P. Balasubramanian, Douglas L. Maskell, Nikos E. Mastorakis
2019	J	`jnl`	Speed and Energy Optimised Quasi-Delay-Insensitive Block Carry Lookahead Adder. CoRR P. Balasubramanian, Douglas L. Maskell, Nikos E. Mastorakis
2019	J	`jnl`	Time-Multiplexed FPGA Overlay Architectures: A Survey. ACM Trans. Design Autom. Electr. Syst. Xiangwei Li, Douglas L. Maskell
2018	J	`jnl`	A Self-Healing Redundancy Scheme for Mission/Safety-Critical Applications. IEEE Access P. Balasubramanian, Douglas L. Maskell
2018	C	`conf`	A System Health Indicator for the Distributed Minority and Majority Voting Based Redundancy Scheme. TENCON P. Balasubramanian, Douglas L. Maskell, Krishnamachar Prasad
2018	A	`conf`	A time-multiplexed FPGA overlay with linear interconnect. DATE Xiangwei Li, Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy
2018	—	`conf`	Asynchronous Early Output Block Carry Lookahead Adder with Improved Quality of Results. MWSCAS P. Balasubramanian, Douglas L. Maskell, Nikos E. Mastorakis
2018	C	`conf`	Hardware Efficient Approximate Adder Design. TENCON P. Balasubramanian, Douglas L. Maskell
2018	—	`conf`	Indicating Asynchronous Multipliers. EECS P. Balasubramanian, Douglas L. Maskell, Nikos E. Mastorakis
2018	—	`conf`	Majority and Minority Voted Redundancy for Safety-Critical Applications. MWSCAS P. Balasubramanian, Douglas L. Maskell, Nikos E. Mastorakis
2017	J	`jnl`	A Hybrid Logic Block Architecture in FPGA for Holistic Efficiency. IEEE Trans. Circuits Syst. II Express Briefs Tao Luo, Hao Liang, Wei Zhang, Bingsheng He, Douglas L. Maskell
2017	A	`conf`	A novel two-stage modular multiplier based on racetrack memory for asymmetric cryptography. ICCAD Tao Luo, Bingsheng He, Wei Zhang, Douglas L. Maskell
2017	J	`jnl`	Approximate Ripple Carry and Carry Lookahead Adders - A Comparative Analysis. CoRR P. Balasubramanian, Cuong Dang, Douglas L. Maskell, K. Prasad
2017	—	`conf`	Approximate quasi-delay-insensitive asynchronous adders: Design and analysis. MWSCAS P. Balasubramanian, Cuong Dang, Douglas L. Maskell
2017	J	`jnl`	Asynchronous Early Output Section-Carry Based Carry Lookahead Adder with Alias Carry Logic. CoRR P. Balasubramanian, Cuong Dang, Douglas L. Maskell, K. Prasad
2017	J	`jnl`	Resource-Aware Just-in-Time OpenCL Compiler for Coarse-Grained FPGA Overlays. CoRR Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy
2016	—	`conf`	A racetrack memory based in-memory booth multiplier for cryptography application. ASP-DAC Tao Luo, Wei Zhang, Bingsheng He, Douglas L. Maskell
2016	J	`jnl`	An Area-Efficient FPGA Overlay using DSP Block based Time-multiplexed Functional Units. CoRR Xiangwei Li, Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy
2016	—	`conf`	Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs? DASC/PiCom/DataCom/CyberSciTech Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy
2016	Misc	`conf`	DeCO: A DSP Block Based FPGA Accelerator Overlay with Low Overhead Interconnect. FCCM Abhishek Kumar Jain, Xiangwei Li, Pranjul Singhai, Douglas L. Maskell, Suhaib A. Fahmy
2016	A	`conf`	Throughput oriented FPGA overlays using DSP blocks. DATE Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy
2015	J	`jnl`	A distributed minority and majority voting based redundancy scheme. Microelectron. Reliab. P. Balasubramanian, Douglas L. Maskell
2015	J	`jnl`	Adapting the DySER Architecture with DSP Blocks as an Overlay for the Xilinx Zynq. SIGARCH Comput. Archit. News Abhishek Kumar Jain, Xiangwei Li, Suhaib A. Fahmy, Douglas L. Maskell
2015	J	`jnl`	An Improved Robust Field-Weakeaning Algorithm for Direct-Torque-Controlled Synchronous-Reluctance-Motor Drives. IEEE Trans. Ind. Electron. Xinan Zhang, Gilbert Hock Beng Foo, D. Mahinda Vilathgamuwa, Douglas L. Maskell
2015	B	`conf`	Automatic fault detection and diagnosis for photovoltaic systems using combined artificial neural network and analytical based methods. IJCNN Lian Lian Jiang, Douglas L. Maskell
2015	Misc	`conf`	Efficient Overlay Architecture Based on DSP Blocks. FCCM Abhishek Kumar Jain, Suhaib A. Fahmy, Douglas L. Maskell
2014	—	`conf`	A uniform implementation scheme for evolutionary optimization algorithms and the experimental implementation of an ACO based MPPT for PV systems under partial shading. CIASG Lian Lian Jiang, Douglas L. Maskell
2014	—	`conf`	HFL micro inverter with front-end diode clamped multi-level inverter and half-wave cycloconverter. ISIE Dulika R. Nayanasiri, D. Mahinda Vilathgamuwa, Douglas L. Maskell
2014	C	`conf`	Soft-switching single inductor current-fed push-pull converter for PV applications. IECON D. R. Nayanasiri, D. Mahinda Vilathgamuwa, Douglas L. Maskell, Gilbert Hock Beng Foo
2014	J	`jnl`	The iDEA DSP Block-Based Soft Processor for FPGAs. ACM Trans. Reconfigurable Technol. Syst. Hui Yan Cheah, Fredrik Brosser, Suhaib A. Fahmy, Douglas L. Maskell
2014	J	`jnl`	Virtualized Execution and Management of Hardware Tasks on a Hybrid ARM-FPGA Platform. J. Signal Process. Syst. Abhishek Kumar Jain, Khoa Dang Pham, Jin Cui, Suhaib A. Fahmy, Douglas L. Maskell
2013	J	`jnl`	A hybrid short read mapping accelerator. BMC Bioinform. Yupeng Chen, Bertil Schmidt, Douglas L. Maskell
2013	C	`conf`	A simple and efficient hybrid maximum power point tracking method for PV systems under partially shaded condition. IECON Lian Lian Jiang, D. R. Nayanasiri, Douglas L. Maskell, D. Mahinda Vilathgamuwa
2013	J	`jnl`	C2FPGA - A dependency-timing graph design methodology. J. Parallel Distributed Comput. Sunita Chandrasekaran, Shilpa Shanbagh, Ramkumar Jayaraman, Douglas L. Maskell, Hui Yan Cheah
2013	C	`conf`	Current-controlled resonant circuit based photovoltaic micro-inverter with half- wave cycloconverter. IAS D. R. Nayanasiri, D. Mahinda Vilathgamuwa, Douglas L. Maskell
2013	C	`conf`	High-frequency-link micro-inverter with front-end current-fed half-bridge boost converter and half-wave cycloconverter. IECON D. R. Nayanasiri, D. Mahinda Vilathgamuwa, Douglas L. Maskell
2013	—	`conf`	Microkernel hypervisor for a hybrid ARM-FPGA platform. ASAP Khoa Dang Pham, Abhishek Kumar Jain, Jin Cui, Suhaib A. Fahmy, Douglas L. Maskell
2013	J	`jnl`	Reconfigurable Accelerator for the Word-Matching Stage of BLASTN. IEEE Trans. Very Large Scale Integr. Syst. Yupeng Chen, Bertil Schmidt, Douglas L. Maskell
2012	J	`jnl`	A Fast High-Level Event-Driven Thermal Estimator for Dynamic Thermal Aware Scheduling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jin Cui, Douglas L. Maskell
2012	Misc	`conf`	A flann-based controller for maximum power point tracking in PV systems under rapidly changing conditions. ICASSP Lian Lian Jiang, Douglas L. Maskell, Jagdish Chandra Patra
2012	A	`conf`	A lean FPGA soft processor built using a DSP block. FPGA Hui Yan Cheah, Suhaib A. Fahmy, Douglas L. Maskell, Chidamber Kulkarni
2012	A	`conf`	Accelerating short read mapping on an FPGA (abstract only). FPGA Yupeng Chen, Bertil Schmidt, Douglas L. Maskell
2012	B	`conf`	An FPGA aligner for short read mapping. FPL Yupeng Chen, Bertil Schmidt, Douglas L. Maskell
2012	J	`jnl`	CUSHAW: a CUDA compatible short read aligner to large genomes based on the Burrows-Wheeler transform. Bioinform. Yongchao Liu, Bertil Schmidt, Douglas L. Maskell
2012	B	`conf`	Chebyshev Functional Link Neural Network-based modeling and experimental verification for photovoltaic arrays. IJCNN Lian Lian Jiang, Douglas L. Maskell, Jagdish Chandra Patra
2012	Misc	`conf`	Fourth Workshop on using Emerging Parallel Architectures. ICCS Bertil Schmidt, Douglas L. Maskell
2012	—	`conf`	iDEA: A DSP block based FPGA soft processor. FPT Hui Yan Cheah, Suhaib A. Fahmy, Douglas L. Maskell
2011	J	`jnl`	A Novel Fuzzy Associative Memory Architecture for Stock Market Prediction and Trading. Int. J. Fuzzy Syst. Appl. Chai Quek, Zaiyi Guo, Douglas L. Maskell
2011	—	`conf`	An Ultrafast Scalable Many-Core Motif Discovery Algorithm for Multiple GPUs. IPDPS Workshops Yongchao Liu, Bertil Schmidt, Douglas L. Maskell
2011	J	`jnl`	CompleteMOTIFs: DNA motif discovery platform for transcription factor binding experiments. Bioinform. Lakshmi Kuttippurathu, Michael Hsing, Yongchao Liu, Bertil Schmidt, Douglas L. Maskell, Kyungjoon Lee, Aibin He, William T. Pu, Sek Won Kong
2011	J	`jnl`	DecGPU: distributed error correction on massively parallel graphics processing units using CUDA and MPI. BMC Bioinform. Yongchao Liu, Bertil Schmidt, Douglas L. Maskell
2011	B	`conf`	Estimation of external quantum efficiency for multi-junction solar cells under influence of charged particles using artificial neural networks. SMC Jagdish Chandra Patra, Lian Lian Jiang, Douglas L. Maskell
2011	J	`jnl`	Parallelized short read assembly of large genomes using de Bruijn graphs. BMC Bioinform. Yongchao Liu, Bertil Schmidt, Douglas L. Maskell
2011	—	`conf`	Performance-Power Design Space Exploration in a Hybrid Computing Platform Suitable for Mobile Applications. ISED Ramkumar Jayaraman, Handi Kartadihardja, Douglas L. Maskell
2011	Misc	`conf`	Third Workshop on using Emerging Parallel Architectures. ICCS Bertil Schmidt, Douglas L. Maskell
2010	A	`conf`	A dependency graph based methodology for parallelizing HLL applications on FPGA (abstract only). FPGA Sunita Chandrasekaran, Shilpa Shanbagh, Douglas L. Maskell
2010	J	`jnl`	An improved common subexpression elimination method for reducing logic operators in FIR filter implementations without increasing logic depth. Integr. Achutavarrier Prasad Vinod, Edmund Ming-Kit Lai, Douglas L. Maskell, Pramod Kumar Meher
2010	J	`jnl`	CUDA-MEME: Accelerating motif discovery in biological sequences using CUDA-enabled graphics processing units. Pattern Recognit. Lett. Yongchao Liu, Bertil Schmidt, Weiguo Liu, Douglas L. Maskell
2010	J	`jnl`	EpiList II: Closing the Loop in the Development of Generic Cognitive Skills. IEEE Trans. Syst. Man Cybern. Part A Ghee Ming Goh, Chai Quek, Douglas L. Maskell
2010	—	`conf`	High level event driven thermal estimation for thermal aware task allocation and scheduling. ASP-DAC Jin Cui, Douglas L. Maskell
2010	J	`jnl`	MSAProbs: multiple sequence alignment based on pair hidden Markov models and partition function posterior probabilities. Bioinform. Yongchao Liu, Bertil Schmidt, Douglas L. Maskell
2010	Misc	`conf`	Second Workshop on using Emerging Parallel Architectures. ICCS Bertil Schmidt, Douglas L. Maskell
2009	—	`conf`	A Reconfigurable Bloom Filter Architecture for BLASTN. ARCS Yupeng Chen, Bertil Schmidt, Douglas L. Maskell
2009	—	`conf`	Dynamic thermal-aware scheduling on chip multiprocessor for soft real-time system. ACM Great Lakes Symposium on VLSI Jin Cui, Douglas L. Maskell
2009	J	`jnl`	High Speed Biological Sequence Analysis With Hidden Markov Models on Reconfigurable Platforms. IEEE Trans. Inf. Technol. Biomed. Timothy F. Oliver, Bertil Schmidt, Yanto Jakop, Douglas L. Maskell
2009	—	`conf`	MSA-CUDA: Multiple Sequence Alignment on Graphics Processing Units with CUDA. ASAP Yongchao Liu, Bertil Schmidt, Douglas L. Maskell
2009	A	`conf`	Parallel reconstruction of neighbor-joining trees for large multiple sequence alignments using CUDA. IPDPS Yongchao Liu, Bertil Schmidt, Douglas L. Maskell
2009	—	`conf`	Workshop on Using Emerging Parallel Architectures for Computational Science. ICCS (1) Bertil Schmidt, Douglas L. Maskell
2008	J	`jnl`	A unified architecture for a public key cryptographic coprocessor. J. Syst. Archit. Yi Wang, Douglas L. Maskell, Jussipekka Leiwo
2008	C	`conf`	Efficient multiplierless channel filters for multi-standard SDR. CIT Douglas L. Maskell, A. Prasad Vinod
2008	C	`conf`	Multiplierless multi-standard SDR channel filters. MMSP Douglas L. Maskell, Achutavarrier Prasad Vinod, Graham S. Woods
2007	B	`conf`	An Embedded Systems graduate education for Singapore. ICPADS Ian McLoughlin, Douglas L. Maskell, Thambipillai Srikanthan, Wooi-Boon Goh
2007	—	`conf`	C-Based Design Methodology for FPGA Implementation of ClustalW MSA. PRIB Yan Lin Aung, Douglas L. Maskell, Timothy F. Oliver, Bertil Schmidt, William Bong
2007	J	`jnl`	Design of efficient multiplierless FIR filters. IET Circuits Devices Syst. Douglas L. Maskell
2007	J	`jnl`	Fast Identification of Custom Instructions for Extensible Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiaoyong Chen, Douglas L. Maskell, Yang Sun
2007	J	`jnl`	Prerouted FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System. EURASIP J. Embed. Syst. Timothy F. Oliver, Douglas L. Maskell
2007	J	`jnl`	Supporting multiple-input, multiple-output custom functions in configurable processors. J. Syst. Archit. Xiaoyong Chen, Douglas L. Maskell
2007	B	`conf`	Type-2 GA-TSK fuzzy neural network. IEEE Congress on Evolutionary Computation Alvin Cai, Chai Quek, Douglas L. Maskell
2006	B	`conf`	A Brain Inspired Fuzzy Neuro-predictor for Bank Failure Analysis. IEEE Congress on Evolutionary Computation Chee H. Lee, Chai Quek, Douglas L. Maskell
2006	J	`jnl`	A technique for expressing IT security objectives. Inf. Softw. Technol. Jussipekka Leiwo, Lam-for Kwok, Douglas L. Maskell, Nenad Stankovic
2006	Misc	`conf`	Accelerating the Viterbi Algorithm for Profile Hidden Markov Models Using Reconfigurable Hardware. International Conference on Computational Science (1) Timothy F. Oliver, Bertil Schmidt, Yanto Jakop, Douglas L. Maskell
2006	J	`jnl`	Adaptive subsample delay estimation using windowed correlation. IEEE Trans. Circuits Syst. II Express Briefs Douglas L. Maskell, Graham S. Woods
2006	—	`conf`	Automatic Identification of Custom Functions for Embedded Processors with MIMO Extensions. APCCAS Xiaoyong Chen, Douglas L. Maskell, Yang Sun
2006	B	`conf`	Execution Objects for Dynamically Reconfigurable FPGA Systems. FPL Timothy F. Oliver, Douglas L. Maskell
2006	B	`conf`	FCMAC-AARS: A Novel FNN Architecture for Stock Market Prediction and Trading. IEEE Congress on Evolutionary Computation Zaiyi Guo, Chai Quek, Douglas L. Maskell
2006	J	`jnl`	High-speed Multiple Sequence Alignment on a reconfigurable platform. Int. J. Bioinform. Res. Appl. Timothy F. Oliver, Bertil Schmidt, Douglas L. Maskell, Darran Nathan, Ralf Clemens
2006	—	`conf`	M ARCS Xiaoyong Chen, Douglas L. Maskell
2006	—	`conf`	Pre-Routed FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System. Dynamically Reconfigurable Architectures Douglas L. Maskell, Timothy F. Oliver
2006	B	`conf`	Software-Oriented Approach to Hardware-Software Co-Simulation for FPGA-Based Risc Extensible Processor. FPL K. S. Tham, Douglas L. Maskell
2006	C	`conf`	The design of multiplierless FIR filters with a minimum adder step and reduced hardware complexity. ISCAS Douglas L. Maskell, Jussipekka Leiwo, Jagdish Chandra Patra
2006	—	`conf`	Unified Signed-Digit Number Adder for RSA and ECC Public-key Cryptosystems. APCCAS Yi Wang, Douglas L. Maskell, Jussipekka Leiwo, Thambipillai Srikanthan
2005	—	`conf`	A reconfigurable architecture for scanning biosequence databases. ISCAS (5) Timothy F. Oliver, Bertil Schmidt, Douglas L. Maskell, Achutavarrier Prasad Vinod
2005	J	`jnl`	Adaptive subsample delay estimation using a modified quadrature phase detector. IEEE Trans. Circuits Syst. II Express Briefs Douglas L. Maskell, Graham S. Woods
2005	—	`conf`	An FPGA Model for Developing Dynamic Circuit Computing. FPT Timothy F. Oliver, Douglas L. Maskell
2005	—	`conf`	Biological Sequence Analysis with Hidden Markov Models on an FPGA. Asia-Pacific Computer Systems Architecture Conference Jacop Yanto, Timothy F. Oliver, Bertil Schmidt, Douglas L. Maskell
2005	A	`conf`	Hyper customized processors for bio-sequence database scanning on FPGAs. FPGA Timothy F. Oliver, Bertil Schmidt, Douglas L. Maskell
2005	—	`conf`	Multiple Sequence Alignment on an FPGA. ICPADS (2) Timothy F. Oliver, Bertil Schmidt, Douglas L. Maskell, Darran Nathan, Ralf Clemens
2005	J	`jnl`	Reconfigurable architectures for bio-sequence database scanning on FPGAs. IEEE Trans. Circuits Syst. II Express Briefs Timothy F. Oliver, Bertil Schmidt, Douglas L. Maskell
2005	—	`conf`	Software-Oriented System-Level Simulation for Design Space Exploration of Reconfigurable Architectures. Asia-Pacific Computer Systems Architecture Conference K. S. Tham, Douglas L. Maskell
2005	J	`jnl`	Using reconfigurable hardware to accelerate multiple sequence alignment with ClustalW. Bioinform. Timothy F. Oliver, Bertil Schmidt, Darran Nathan, Ralf Clemens, Douglas L. Maskell
2004	—	`conf`	A hardware efficient implementation of an adaptive subsample delay estimator. ISCAS (3) Douglas L. Maskell, Graham S. Woods, Andrew Kerans
2003	—	`conf`	Towards Run-Time Re-Configurable Techniques for Real-Time Embedded Applications. Engineering of Reconfigurable Systems and Algorithms Timothy F. Oliver, Douglas L. Maskell
2002	J	`jnl`	The discrete-time quadrature subsample estimation of delay. IEEE Trans. Instrum. Meas. Douglas L. Maskell, Graham S. Woods
2000	J	`jnl`	A frequency modulated envelope delay FSCW radar for multiple-target applications. IEEE Trans. Instrum. Meas. Douglas L. Maskell, Graham S. Woods
1999	J	`jnl`	The estimation of subsample time delay of arrival in the discrete-time measurement of phase delay. IEEE Trans. Instrum. Meas. Douglas L. Maskell, Graham S. Woods