Doug A. Edwards

25 papers A 3C 6Misc 2Journal 6Unranked 8
YearRankTypeTitle / Venue / Authors
2015 A conf
De-elastisation: from asynchronous dataflows to synchronous circuits.
DATE
Mahdi Jelodari Mamaghani, Jim D. Garside, Doug A. Edwards
2014 C conf
Automatic data path extraction in large-scale register-transfer level designs.
ISCAS
Wei Song, Jim D. Garside, Doug A. Edwards
2014 C conf
Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA.
DSD
Mahdi Jelodari Mamaghani, Jim D. Garside, William B. Toms, Doug A. Edwards
2013 J jnl
Computational Performance Optimisation for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits.
VLSI Design
Zheng Xie, Doug A. Edwards
2012 A conf
Area efficient asynchronous SDM routers using 2-stage Clos switches.
DATE
Wei Song, Doug A. Edwards, Jim D. Garside, William J. Bainbridge
2011 J jnl
Asynchronous spatial division multiplexing router.
Microprocess. Microsystems
Wei Song, Doug A. Edwards
2010 — conf
A low latency wormhole router for asynchronous on-chip networks.
ASP-DAC
Wei Song, Doug A. Edwards
2010 — conf
An Asynchronous Routing Algorithm for Clos Networks.
ACSD
Wei Song, Doug A. Edwards
2010 J jnl
Asynchronous Data-Driven Circuit Synthesis.
IEEE Trans. Very Large Scale Integr. Syst.
Sam Taylor, Doug A. Edwards, Luis A. Plana, Luis A. Tarazona
2010 C conf
Computation reduction for statistical analysis of the effect of nano-CMOS variability on asynchronous circuits.
DDECS
Zheng Xie, Doug A. Edwards
2010 C conf
Description-Level Optimisation of Synthesisable Asynchronous Circuits.
DSD
Luis A. Tarazona, Doug A. Edwards, Andrew Bardsley, Luis A. Plana
2009 C conf
A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor.
DSD
Luis A. Tarazona, Doug A. Edwards, Luis A. Plana
2009 — conf
Adaptive stochastic routing in fault-tolerant on-chip networks.
NOCS
Wei Song, Doug A. Edwards, José Luis Núñez-Yáñez, Sohini Dasgupta
2009 — conf
Building asynchronous routers with independent sub-channels.
SoC
Wei Song, Doug A. Edwards
2009 — conf
Dual-Sum Single-Carry Self-Timed Adder Designs.
ISVLSI
P. Balasubramanian, Doug A. Edwards
2009 — conf
Prime Indicants: A Synthesis Method for Indicating Combinational Logic Blocks.
ASYNC
William B. Toms, Doug A. Edwards
2009 — conf
Teak: A Token-Flow Implementation for the Balsa Language.
ACSD
Andrew Bardsley, Luis A. Tarazona, Doug A. Edwards
2008 J jnl
Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems.
IET Comput. Digit. Tech.
José L. Núñez-Yáñez, Doug A. Edwards, Antonio Marcello Coppola
2008 — conf
Automatic Compilation of Data-Driven Circuits.
ASYNC
Sam Taylor, Doug A. Edwards, Luis A. Plana
2007 Misc conf
Performance-driven syntax-directed synthesis of asynchronous processors.
CASES
Luis A. Plana, Doug A. Edwards, Sam Taylor, Luis A. Tarazona, Andrew Bardsley
2005 C conf
Attacking Control Overhead to Improve Synthesised Asynchronous Circuit Performance.
ICCD
Luis A. Plana, Sam Taylor, Doug A. Edwards
2005 Misc conf
Synthesis of Asynchronous Circuits Using Early Data Validity.
VLSI Design
Nitin Gupta, Doug A. Edwards
2002 A conf
A Burst-Mode Oriented Back-End for the Balsa Synthesis System.
DATE
Tiberiu Chelcea, Steven M. Nowick, Andrew Bardsley, Doug A. Edwards
2002 J jnl
Balsa: An Asynchronous Hardware Synthesis Language.
Comput. J.
Doug A. Edwards, Andrew Bardsley
2000 J jnl
Synthesising an asynchronous DMA controller with Balsa.
J. Syst. Archit.
Andrew Bardsley, Doug A. Edwards