Doru-Florin Chiper

24 papers A 3C 1Journal 13Unranked 7
YearRankTypeTitle / Venue / Authors
2023 J jnl
Analytic Design Technique for 2D FIR Circular Filter Banks and Their Efficient Implementation Using Polyphase Approach.
Sensors
Radu Matei, Doru-Florin Chiper
2023 J jnl
New Systolic Array Algorithms and VLSI Architectures for 1-D MDST.
Sensors
Doru-Florin Chiper, Arcadie Cracan
2023 A conf
Polyphase Implementation for Gaussian 2D FIR Filters with Circular Symmetry.
ECAI
Doru-Florin Chiper, Radu Matei
2023 J jnl
x-DTT: A package for calculating real and Integer Discrete Tchebichef Transform kernels based on orthogonal polynomials.
SoftwareX
Ahcen Aliouat, Nasreddine Kouadria, Doru-Florin Chiper
2022 — conf
A New Integer Algorithm for a VLSI Implementation of DCT Using Obfuscation Technique.
COMM
Doru-Florin Chiper, Arcadie Cracan
2022 A conf
An Improved Algorithm for an Efficient VLSI Implementation of Type IV DST using Short Quasi-Band Correlation Structures.
ECAI
Doru-Florin Chiper, Laura-Teodora Cotorobai
2022 — conf
An Improved Algorithm for the VLSI Implementation of Type II Generalized DHT that Allows an Efficient Incorporation of Obfuscation Technique.
TSP
Doru-Florin Chiper
2021 J jnl
A Structured Fast Algorithm for the VLSI Pipeline Implementation of Inverse Discrete Cosine Transform.
Circuits Syst. Signal Process.
Doru-Florin Chiper
2020 — conf
A New VLSI Algorithm for an Efficient VLSI Implementation of Type IV DST based on Short Band- Correlation Structures.
COMM
Doru-Florin Chiper, Laura-Teodora Cotorobai
2020 — conf
A New VLSI Algorithm for type IV DCT for an Efficient Implementation of Obfuscation Technique.
TSP
Laura-Teodora Cotorobai, Doru-Florin Chiper
2018 J jnl
A Structured Dual Split-Radix Algorithm for the Discrete Hartley Transform of Length \(2^{N}\).
Circuits Syst. Signal Process.
Doru-Florin Chiper
2018 A conf
A Unified VLSI architecture for 1D IDCT and IDST based on pseudo-band correlations.
ECAI
Doru-Florin Chiper, Laura-Teodora Cotorobai
2016 — conf
A new VLSI algorithm for a high-throughput implementation of type IV DCT.
COMM
Doru-Florin Chiper
2013 J jnl
A Novel VLSI DHT Algorithm for a Highly Modular and Parallel Architecture.
IEEE Trans. Circuits Syst. II Express Briefs
Doru-Florin Chiper
2012 J jnl
Radix-2 Fast Algorithm for Computing Discrete Hartley Transform of Type III.
IEEE Trans. Circuits Syst. II Express Briefs
Doru-Florin Chiper
2011 J jnl
A new VLSI algorithm and architecture for the hardware implementation of type IV discrete cosine transform using a pseudo-band correlation structure.
Central Eur. J. Comput. Sci.
Doru-Florin Chiper
2011 J jnl
Fast Radix-2 Algorithm for the Discrete Hartley Transform of Type II.
IEEE Signal Process. Lett.
Doru-Florin Chiper
2011 J jnl
Novel VLSI Algorithm and Architecture with Good Quantization Properties for a High-Throughput Area Efficient Systolic Array Implementation of DCT.
EURASIP J. Adv. Signal Process.
Doru-Florin Chiper, Paul Ungureanu
2008 — conf
A new systolic array algorithm for a high throughput low cost VLSI implementation of DCT.
ICECS
Doru-Florin Chiper, M. N. S. Swamy, M. Omair Ahmad
2007 J jnl
An Efficient Unified Framework for Implementation of a Prime-Length DCT/IDCT With High Throughput.
IEEE Trans. Signal Process.
Doru-Florin Chiper, M. N. S. Swamy, M. Omair Ahmad
2005 J jnl
Systolic algorithms and a memory-based design approach for a unified architecture for the computation of DCT/DST/IDCT/IDST.
IEEE Trans. Circuits Syst. I Regul. Pap.
Doru-Florin Chiper, M. N. Srikanta Swamy, M. Omair Ahmad, Thanos Stouraitis
2002 J jnl
A systolic array architecture for the discrete sine transform.
IEEE Trans. Signal Process.
Doru-Florin Chiper, M. N. S. Swamy, M. Omair Ahmad, Thanos Stouraitis
1999 — conf
A Systolic Array Algorithm for an Efficient Unified Memory-Based Implementation of the Inverse Discrete Cosine and Sine Transforms.
ICIP (2)
Doru-Florin Chiper
1997 C conf
A new systolic array algorithm for memory-based VLSI array implementation of DCT.
ISCC
Doru-Florin Chiper