Dongsuk Shin

19 papers C 2Journal 11Unranked 6
YearRankTypeTitle / Venue / Authors
2023 J jnl
Fully Automated Hardware-Driven Clock-Gating Architecture With Complete Clock Coverage for 4 nm Exynos Mobile SOC.
IEEE J. Solid State Circuits
Jae-Gon Lee, Younsik Choi, Hoyeon Jeon, Jong-Jin Lee, Dongsuk Shin
2022 J jnl
An Energy-Efficient DRAM Cache Architecture for Mobile Platforms With PCM-Based Main Memory.
ACM Trans. Embed. Comput. Syst.
Dongsuk Shin, Hakbeom Jang, Kiseok Oh, Jae W. Lee
2020 — conf
2.4 A 7nm High-Performance and Energy-Efficient Mobile Application Processor with Tri-Cluster CPUs and a Sparsity-Aware NPU.
ISSCC
Young-Duk Kim, Wookyeong Jeong, Lakkyung Jung, Dongsuk Shin, Jae Geun Song, Jinook Song, Hyeokman Kwon, Jaeyoung Lee, Jaesu Jung, Myungjin Kang, Jaehun Jeong, Yoonjoo Kwon, Nak Hee Seong
2018 C conf
Bandwidth-aware DRAM page migration for heterogeneous mobile memory systems.
ICCE
Dongsuk Shin, Jae W. Lee
2018 J jnl
Erratum: Energy-efficient heterogeneous memory system for mobile platforms [IEICE Electronics Express Vol. 14 (2017) No. 24 pp. 20171002].
IEICE Electron. Express
Dongsuk Shin, Hakbeom Jang, Jae W. Lee
2017 J jnl
Energy-efficient heterogeneous memory system for mobile platforms.
IEICE Electron. Express
Dongsuk Shin, Hakbeom Jang, Jae W. Lee
2011 J jnl
A 3.57 Gb/s/pin Low Jitter All-Digital DLL With Dual DCC Circuit for GDDR3 DRAM in 54-nm CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst.
Won-Joo Yun, Hyun-Woo Lee, Dongsuk Shin, Suki Kim
2010 — conf
Frequency-independent fast-lock register-controlled DLL with wide-range duty cycle adjuster.
SoCC
Dongsuk Shin, Joo-Hwan Cho, Young-Jung Choi, Byong-Tae Chung
2009 J jnl
A 7 ps Jitter 0.053 mm
IEEE J. Solid State Circuits
Dongsuk Shin, Janghoon Song, Hyunsoo Chae, Chulwoo Kim
2009 C conf
A Fast-lock Synchronous Multi-phase Clock Generator based on a Time-to-digital Converter.
ISCAS
Dongsuk Shin, Jabeom Koo, Won-Joo Yun, Young-Jung Choi, Chulwoo Kim
2009 J jnl
A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time.
IEEE Trans. Very Large Scale Integr. Syst.
Moo-young Kim, Dongsuk Shin, Hyunsoo Chae, Chulwoo Kim
2009 J jnl
Coverage expandable current type code controlled DCC with TDC-based range selector.
IEICE Electron. Express
Won-Joo Yun, Hyun-Woo Lee, Dongsuk Shin, Young-Jung Choi, Suki Kim
2008 — conf
A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology.
ISSCC
Won-Joo Yun, Hyun-Woo Lee, Dongsuk Shin, Shin-Deok Kang, Ji-Yeon Yang, Hyeng-Ouk Lee, Dong-Uk Lee, Sujeong Sim, Young-Ju Kim, Won-Jun Choi, Keun-Soo Song, Sang-Hoon Shin, Hyang-Hwa Choi, Hyung-Wook Moon, Seung-Wook Kwack, Jung-Woo Lee, Young-Kyoung Choi, Nak-Kyu Park, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Ye Seok Yang
2008 — conf
A 0.17-1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme.
ESSCIRC
Dongsuk Shin, Won-Joo Yun, Hyun-Woo Lee, Young-Jung Choi, Suki Kim, Chulwoo Kim
2008 J jnl
A 4-bit 2GSamples/s parallel Flash ADC using comb-type reference ladder.
IEICE Electron. Express
Won-Joo Yun, Dongsuk Shin, Suki Kim
2008 J jnl
Wide frequency range duty cycle correction circuit for DDR interface.
IEICE Electron. Express
Dongsuk Shin, Soo-Won Kim, Chulwoo Kim
2007 — conf
A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC.
ISSCC
Dongsuk Shin, Janghoon Song, Hyunsoo Chae, Kwan-Weon Kim, Young-Jung Choi, Chulwoo Kim
2007 — conf
A Low-Jitter Open-Loop All-Digital Clock Generator with 2 Cycle Lock-Time.
CICC
Moo-young Kim, Dongsuk Shin, Hyunsoo Chae, Sunghwa Ok, Chulwoo Kim
2006 J jnl
A New Energy x Delay-Aware Flip-Flop.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Inhwa Jung, Moo-young Kim, Dongsuk Shin, Seon Wook Kim, Chulwoo Kim