Dong-U Lee

33 papers A* 1B 3Misc 3Journal 19Unranked 6
YearRankTypeTitle / Venue / Authors
2015 J jnl
Automated Iterative Pipelining for ASIC Design.
ACM Trans. Design Autom. Electr. Syst.
Lok-Won Kim, Dong-U Lee, John D. Villasenor
2012 J jnl
Precision-Aware Self-Quantizing Hardware Architectures for the Discrete Wavelet Transform.
IEEE Trans. Image Process.
Dong-U Lee, Lok-Won Kim, John D. Villasenor
2009 J jnl
Energy-Efficient Image Compression for Resource-Constrained Platforms.
IEEE Trans. Image Process.
Dong-U Lee, Hyungjin Kim, Mohammad H. Rahimi, Deborah Estrin, John D. Villasenor
2009 J jnl
Hierarchical Segmentation for Hardware Function Evaluation.
IEEE Trans. Very Large Scale Integr. Syst.
Dong-U Lee, Ray C. C. Cheung, Wayne Luk, John D. Villasenor
2009 J jnl
Optimized Custom Precision Function Evaluation for Embedded Processors.
IEEE Trans. Computers
Dong-U Lee, John D. Villasenor
2008 J jnl
Design Tradeoffs and Hardware Architecture for Real-Time Iterative MIMO Detection using Sphere Decoding and LDPC Coding.
IEEE J. Sel. Areas Commun.
Hyungjin Kim, Dong-U Lee, John D. Villasenor
2008 J jnl
Energy-Aware High Resolution Image Acquisition via Heterogeneous Image Sensors.
IEEE J. Sel. Top. Signal Process.
Hyungjin Kim, Mohammad H. Rahimi, Dong-U Lee, Deborah Estrin, John D. Villasenor
2008 J jnl
Hardware Implementation Trade-Offs of Polynomial Approximations and Interpolations.
IEEE Trans. Computers
Dong-U Lee, Ray C. C. Cheung, Wayne Luk, John D. Villasenor
2008 J jnl
Pilotless Frame Synchronization for LDPC-Coded Transmission Systems.
IEEE Trans. Signal Process.
Dong-U Lee, Hyungjin Kim, Christopher R. Jones, John D. Villasenor
2007 J jnl
A Bit-Width Optimization Methodology for Polynomial-Based Function Evaluation.
IEEE Trans. Computers
Dong-U Lee, John D. Villasenor
2007 J jnl
A Flexible Architecture for Precise Gamma Correction.
IEEE Trans. Very Large Scale Integr. Syst.
Dong-U Lee, Ray C. C. Cheung, John D. Villasenor
2007 — conf
Energy-optimized image communication on resource-constrained sensor platforms.
IPSN
Dong-U Lee, Hyungjin Kim, Steven Tu, Mohammad H. Rahimi, Deborah Estrin, John D. Villasenor
2007 J jnl
Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method.
IEEE Trans. Very Large Scale Integr. Syst.
Ray C. C. Cheung, Dong-U Lee, Wayne Luk, John D. Villasenor
2007 J jnl
Pilotless Frame Synchronization via LDPC Code Constraint Feedback.
IEEE Commun. Lett.
Dong-U Lee, Hyungjin Kim, Christopher R. Jones, John D. Villasenor
2006 J jnl
A Hardware Gaussian Noise Generator Using the Box-Muller Method and Its Error Analysis.
IEEE Trans. Computers
Dong-U Lee, John D. Villasenor, Wayne Luk, Philip Heng Wai Leong
2006 J jnl
Accuracy-Guaranteed Bit-Width Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Dong-U Lee, Altaf Abdul Gaffar, Ray C. C. Cheung, Oskar Mencer, Wayne Luk, George A. Constantinides
2006 — conf
Inversion-based hardware gaussian random number generator: A case study of function evaluation via hierarchical segmentation.
FPT
Dong-U Lee, Ray C. C. Cheung, John D. Villasenor, Wayne Luk
2006 J jnl
Joint LDPC decoding and timing recovery using code constraint feedback.
IEEE Commun. Lett.
Dong-U Lee, Esteban L. Vallés, John D. Villasenor, Christopher R. Jones
2005 J jnl
A hardware Gaussian noise generator using the Wallace method.
IEEE Trans. Very Large Scale Integr. Syst.
Dong-U Lee, Wayne Luk, John D. Villasenor, Guanglie Zhang, Philip Heng Wai Leong
2005 Misc conf
Automating custom-precision function evaluation for embedded processors.
CASES
Ray C. C. Cheung, Dong-U Lee, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung
2005 A* conf
MiniBit: bit-width optimization via affine arithmetic.
DAC
Dong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk
2005 J jnl
Optimizing Hardware Function Evaluation.
IEEE Trans. Computers
Dong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk
2005 — conf
Reconfigurable Acceleration for Monte Carlo Based Financial Simulation.
FPT
Guanglie Zhang, Philip Heng Wai Leong, Chun Hok Ho, Kuen Hung Tsoi, Chris C. C. Cheung, Dong-U Lee, Ray C. C. Cheung, Wayne Luk
2005 B conf
Ziggurat-based Hardware Gaussian Random Number Generator.
FPL
Guanglie Zhang, Philip Heng Wai Leong, Dong-U Lee, John D. Villasenor, Ray C. C. Cheung, Wayne Luk
2004 Misc conf
A Flexible Hardware Encoder for Low-Density Parity-Check Codes.
FCCM
Dong-U Lee, Wayne Luk, Connie Wang, Christopher R. Jones, Michael Smith, John D. Villasenor
2004 J jnl
A Gaussian Noise Generator for Hardware-Based Simulations.
IEEE Trans. Computers
Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung
2004 — conf
Adaptive range reduction for hardware function evaluation.
FPT
Dong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk
2004 B conf
Automating Optimized Table-with-Polynomial Function Evaluation for FPGAs.
FPL
Dong-U Lee, Oskar Mencer, David J. Pearce, Wayne Luk
2004 — —
Hardware designs for function evaluation and LDPC coding.
Dong-U Lee
2003 Misc conf
A Hardware Gaussian Noise Generator for Channel Code Evaluation.
FCCM
Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung
2003 — conf
Hierarchical segmentation schemes for function evaluation.
FPT
Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung
2003 B conf
Non-uniform Segmentation for Hardware Function Evaluation.
FPL
Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung
2002 — conf
Incremental programming for reconfigurable engines.
FPT
Dong-U Lee, T. K. Lee, Wayne Luk, Peter Y. K. Cheung