Dong-Hoon Jung

27 papers C 1Misc 1Journal 18Unranked 7
YearRankTypeTitle / Venue / Authors
2025 — conf
8.4 A 4GHz, 0.69%-Accuracy Voltage-Droop Detector with Multiple Remote Sensing and Under 2-Cycle Detection Latency in 2nm GAAFET.
ISSCC
Dong-Hoon Jung, Dongha Lee, Seki Kim, Susie Kim, Min Young Kang, Takahiro Nomiyama, Dongsu Kim, Jongwoo Lee
2025 J jnl
Design of Coil Patterns for an Axial Flux Permanent Magnet Synchronous Motor With PCB Stator.
IEEE Access
Dong-Woo Nam, Min-Ki Hong, Na-Rim Jo, Dong-Hoon Jung, Won-Ho Kim
2024 — conf
14.6 A 10A Computational Digital LDO Achieving 263A/mm
ISSCC
Dongha Lee, Seki Kim, Takahiro Nomiyama, Dong-Hoon Jung, Dongsu Kim, Jongwoo Lee, Sungung Kwak
2023 J jnl
A Study on Design Method of Synchronous Reluctance Motor Based on Nonlinear MEC Using Newton-Raphson Method.
IEEE Access
Dong-Hoon Jung, Ki-Deok Lee, Jae-Kwang Lee
2023 J jnl
A Study on the Control Method of 6-DOF Magnetic Levitation System Using Non-Contact Position Sensors.
Sensors
Dong-Hoon Jung, Jong Suk Lim
2021 — conf
29.6 A Distributed Digital LDO with Time-Multiplexing Calibration Loop Achieving 40A/mm2 Current Density and 1mA-to-6.4A Ultra-Wide Load Range in 5nm FinFET CMOS.
ISSCC
Dong-Hoon Jung, Tae-Hwang Kong, Jun-Hyeok Yang, Sangho Kim, Kwangho Kim, Jeongpyo Park, Michael Choi, Jongshin Shin
2019 Misc conf
Lessons Learned from an Auditory-vibrotactile Sensory Experience in the Museum.
ISS
Dong-Hoon Jung, Jieun Kim, Jeong-Gu Lee, Hoi Jeong Yang, Hokyoung Ryu
2018 J jnl
0.293-mm
IEEE J. Solid State Circuits
Dong-Hoon Jung, Ki-Ryong Kim, Sunghwan Jo, Seong-Ook Jung
2018 J jnl
All-Digital Process-Variation-Calibrated Timing Generator for ATE With 1.95-ps Resolution and Maximum 1.2-GHz Test Rate.
IEEE Trans. Very Large Scale Integr. Syst.
Dong-Hoon Jung, Kyungho Ryu, Jung-Hyun Park, Seong-Ook Jung
2017 J jnl
GRO-TDC with gate-switch-based delay cell halving resolution limit.
Int. J. Circuit Theory Appl.
Jung-Hyun Park, Dong-Hoon Jung, Seong-Ook Jung
2016 J jnl
All-Digital 90° Phase-Shift DLL With Dithering Jitter Suppression Scheme.
IEEE Trans. Very Large Scale Integr. Syst.
Dong-Hoon Jung, Kyungho Ryu, Jung-Hyun Park, Seong-Ook Jung
2016 J jnl
All-Digital ON-Chip Process Sensor Using Ratioed Inverter-Based Ring Oscillator.
IEEE Trans. Very Large Scale Integr. Syst.
Young-Jae An, Dong-Hoon Jung, Kyungho Ryu, Hyuck-Sang Yim, Seong-Ook Jung
2016 J jnl
High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator.
IEEE Trans. Very Large Scale Integr. Syst.
Kyungho Ryu, Jiwan Jung, Dong-Hoon Jung, Jin Hyuk Kim, Seong-Ook Jung
2016 J jnl
Thermal and solar energy harvesting boost converter with time-multiplexing MPPT algorithm.
IEICE Electron. Express
Dong-Hoon Jung, Ki-Ryong Kim, Seong-Ook Jung
2015 J jnl
All-Digital Fast-Locking Delay-Locked Loop Using a Cyclic-Locking Loop for DRAM.
IEEE Trans. Circuits Syst. II Express Briefs
Dong-Hoon Jung, Young-Jae An, Kyungho Ryu, Jung-Hyun Park, Seong-Ook Jung
2015 J jnl
An Energy-Efficient All-Digital Time-Domain-Based CMOS Temperature Sensor for SoC Thermal Management.
IEEE Trans. Very Large Scale Integr. Syst.
Young-Jae An, Dong-Hoon Jung, Kyungho Ryu, Seung-Han Woo, Seong-Ook Jung
2015 J jnl
Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs.
IEEE Trans. Very Large Scale Integr. Syst.
Jung-Hyun Park, Heechai Kang, Dong-Hoon Jung, Kyungho Ryu, Seong-Ook Jung
2014 J jnl
Process-Variation-Calibrated Multiphase Delay Locked Loop With a Loop-Embedded Duty Cycle Corrector.
IEEE Trans. Circuits Syst. II Express Briefs
Kyungho Ryu, Dong-Hoon Jung, Seong-Ook Jung
2013 C conf
A 0.67nJ/S time-domain temperature sensor for low power on-chip thermal management.
ICCE
Young-Jae An, Kyungho Ryu, Dong-Hoon Jung, Seung-Han Woo, Seong-Ook Jung
2013 J jnl
ADDLL for Clock-Deskew Buffer in High-Performance SoCs.
IEEE Trans. Very Large Scale Integr. Syst.
Jung-Hyun Park, Dong-Hoon Jung, Kyungho Ryu, Seong-Ook Jung
2013 — conf
All-digital 90° phase-shift DLL with a dithering jitter suppression scheme.
CICC
Dong-Hoon Jung, Kyungho Ryu, Jung-Hyun Park, Won Lee, Seong-Ook Jung
2013 — conf
All-digital process-variation-calibrated timing generator for ATE with 1.95-ps resolution and a maximum 1.2-GHz test rate.
ESSCIRC
Kyungho Ryu, Dong-Hoon Jung, Seong-Ook Jung
2012 J jnl
A DLL With Dual Edge Triggered Phase Detector for Fast Lock and Low Jitter Clock Generator.
IEEE Trans. Circuits Syst. I Regul. Pap.
Kyungho Ryu, Dong-Hoon Jung, Seong-Ook Jung
2012 — conf
A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction.
ESSCIRC
Dong-Hoon Jung, Kyungho Ryu, Jung-Hyun Park, Seong-Ook Jung
2012 — conf
Integration of dual channel timing formatter system for high speed memory test equipment.
ISOCC
Jaeseok Park, Ingeol Lee, Young-Seok Park, Sung-Geun Kim, Kyungho Ryu, Dong-Hoon Jung, Kangwook Jo, Choong Keun Lee, Hongil Yoon, Seong-Ook Jung, Woo-Young Choi, Sungho Kang
2012 J jnl
Process Variation Tolerant All-Digital 90° Phase Shift DLL for DDR3 Interface.
IEEE Trans. Circuits Syst. I Regul. Pap.
Heechai Kang, Kyungho Ryu, Dong-Hoon Jung, Donghwan Lee, Won Lee, Suho Kim, JongRyun Choi, Seong-Ook Jung
2010 J jnl
A 90° phase-shift DLL with closed-loop DCC for high-speed mobile DRAM interface.
IEEE Trans. Consumer Electron.
Dong-Hoon Jung, Kyungho Ryu, Seong-Ook Jung