Donald E. Thomas

95 papers A* 29A 14C 3Misc 6Journal 25Unranked 16

Year	Rank	Type	Title / Venue / Authors
2017	—	`conf`	Random Forest Architectures on FPGA for Multiple Applications. ACM Great Lakes Symposium on VLSI Xiang Lin, R. D. (Shawn) Blanton, Donald E. Thomas
2015	—	`conf`	Keynote speaker moving digital system design courses into the modern era, again. MSE Donald E. Thomas
2015	A	`conf`	Statistical Learning in Chip (SLIC). ICCAD Ronald D. Blanton, Xin Li, Ken Mai, Diana Marculescu, Radu Marculescu, Jeyanandh Paramesh, Jeff G. Schneider, Donald E. Thomas
2014	J	`jnl`	Cost-effective lifetime and yield optimization for NoC-based MPSoCs. ACM Trans. Design Autom. Electr. Syst. Brett H. Meyer, Adam S. Hartman, Donald E. Thomas
2014	—	`conf`	Low-power hardware implementation of movement decoding for brain computer interface with reduced-resolution discrete cosine transform. EMBC Minho Won, Hassan Albalawi, Xin Li, Donald E. Thomas
2014	—	`conf`	SLIC: Statistical learning in chip. ISIC Ronald D. Blanton, Xin Li, Ken Mai, Diana Marculescu, Radu Marculescu, Jeyanandh Paramesh, Jeff G. Schneider, Donald E. Thomas
2014	—	`conf`	Ultra-low-power biomedical circuit design and optimization: Catching the don't cares. ISIC Xin Li, Ronald Shawn Blanton, Pulkit Grover, Donald E. Thomas
2012	Misc	`conf`	Lifetime improvement through runtime wear-based task mapping. CODES+ISSS Adam S. Hartman, Donald E. Thomas
2010	Misc	`conf`	A case for lifetime-aware task mapping in embedded chip multiprocessors. CODES+ISSS Adam S. Hartman, Donald E. Thomas, Brett H. Meyer
2010	A	`conf`	Cost-effective slack allocation for lifetime improvement in NoC-based MPSoCs. DATE Brett H. Meyer, Adam S. Hartman, Donald E. Thomas
2010	—	`conf`	Slack allocation for yield improvement in NoC-based MPSoCs. ISQED Brett H. Meyer, Adam S. Hartman, Donald E. Thomas
2010	J	`jnl`	Stochastic Contention Level Simulation for Single-Chip Heterogeneous Multiprocessors. IEEE Trans. Computers Alex Bobrek, JoAnn M. Paul, Donald E. Thomas
2009	J	`jnl`	Rethinking the synthesis of buses, data mapping, and memory allocation for MPSoC. Des. Autom. Embed. Syst. Brett H. Meyer, Donald E. Thomas
2007	Misc	`conf`	Event-based re-training of statistical contention models for heterogeneous multiprocessors. CODES+ISSS Alex Bobrek, JoAnn M. Paul, Donald E. Thomas
2007	A	`conf`	Rethinking Automated Synthesis of MPSoC Architectures. IPDPS Brett H. Meyer, Donald E. Thomas
2007	A*	`conf`	Shared Resource Access Attributes for High-Level Contention Models. DAC Alex Bobrek, JoAnn M. Paul, Donald E. Thomas
2007	Misc	`conf`	Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC. CODES+ISSS Brett H. Meyer, Donald E. Thomas
2006	J	`jnl`	Scenario-oriented design for single-chip heterogeneous multiprocessors. IEEE Trans. Very Large Scale Integr. Syst. JoAnn M. Paul, Donald E. Thomas, Alex Bobrek
2005	J	`jnl`	High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors. ACM Trans. Design Autom. Electr. Syst. JoAnn M. Paul, Donald E. Thomas, Andrew S. Cassidy
2005	J	`jnl`	Undergraduate embedded system education at Carnegie Mellon. ACM Trans. Embed. Comput. Syst. Philip Koopman, Howie Choset, Rajeev Gandhi, Bruce H. Krogh, Diana Marculescu, Priya Narasimhan, JoAnn M. Paul, Ragunathan Rajkumar, Daniel P. Siewiorek, Asim Smailagic, Peter Steenkiste, Donald E. Thomas, Chenxi Wang
2004	Misc	`conf`	Benchmark-based design strategies for single chip heterogeneous multiprocessors. CODES+ISSS JoAnn M. Paul, Donald E. Thomas, Alex Bobrek
2004	A*	`conf`	High level cache simulation for heterogeneous multiprocessors. DAC Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Donald E. Thomas, Faraydon Karim
2004	A	`conf`	Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach. DATE Alex Bobrek, Joshua J. Pieper, Jeffrey E. Nelson, JoAnn M. Paul, Donald E. Thomas
2003	A	`conf`	Layered, Multi-Threaded, High-Level Performance Design. DATE Andrew S. Cassidy, JoAnn M. Paul, Donald E. Thomas
2003	A*	`conf`	Schedulers as model-based design elements in programmable heterogeneous multiprocessors. DAC JoAnn M. Paul, Alex Bobrek, Jeffrey E. Nelson, Joshua J. Pieper, Donald E. Thomas
2002	A	`conf`	A Layered, Codesign Virtual Machine Approach to Modeling Computer Systems. DATE JoAnn M. Paul, Donald E. Thomas
2002	A	`conf`	Multi-Level Modeling of Software on Hardware in Concurrent Computation. IPDPS JoAnn M. Paul, Arne J. Suppé, Henele I. Adams, Donald E. Thomas
2002	—	`conf`	System-Level Modeling of a Network Switch SoC. ISSS Andrew S. Cassidy, Christopher P. Andrews, Donald E. Thomas, JoAnn M. Paul
2002	—	`conf`	The design context of concurrent computation systems. CODES JoAnn M. Paul, Christopher M. Eatedali, Donald E. Thomas
2001	J	`jnl`	Co-RAM: combinational logic synthesis applied to software partitions for mapping to a novel memory device. IEEE Trans. Very Large Scale Integr. Syst. Sandra J. Weber, JoAnn M. Paul, Donald E. Thomas
2001	—	`conf`	Modeling and evaluation of hardware/software designs. CODES Neal K. Tibrewala, JoAnn M. Paul, Donald E. Thomas
2001	—	`conf`	Modeling and simulation of steady state and transient behaviors for emergent SoCs. ISSS JoAnn M. Paul, Arne J. Suppé, Donald E. Thomas
2000	A*	`conf`	A codesign virtual machine for hierarchical, balanced hardware/software system modeling. DAC JoAnn M. Paul, Simon N. Peffers, Donald E. Thomas
2000	—	`conf`	Frequency interleaving as a codesign scheduling paradigm. CODES JoAnn M. Paul, Simon N. Peffers, Donald E. Thomas
2000	J	`jnl`	Memory modeling for system synthesis. IEEE Trans. Very Large Scale Integr. Syst. Sari L. Coumeri, Donald E. Thomas
2000	A*	`conf`	Unifying behavioral synthesis and physical design. DAC William E. Dougherty, Donald E. Thomas
1999	C	`conf`	An Environment for Exploring Low Power Memory Configurations in System Level Design. ICCD Sari L. Coumeri, Donald E. Thomas
1999	A	`conf`	Modeling and automating selection of guarding techniques for datapath elements. ISLPED William E. Dougherty, Donald E. Thomas
1999	—	`conf`	Peer-based multithreaded executable co-specification. CODES Donald E. Thomas, JoAnn M. Paul, Simon N. Peffers, Sandra J. Weber
1999	J	`jnl`	Subsetting Behavioral Intellectual Property for Low Power ASIP Design. J. VLSI Signal Process. William E. Dougherty, David J. Pursley, Donald E. Thomas
1999	A*	`conf`	Vertical Benchmarks for CAD. DAC Christopher Inacio, Herman Schmit, David Nagle, Andrew Ryan, Donald E. Thomas, Yingfai Tong, Ben Klass
1998	J	`jnl`	Address generation for memories containing multiple arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Herman Schmit, Donald E. Thomas
1998	A	`conf`	Managing Pipeline-Reconfigurable FPGAs. FPGA Srihari Cadambi, Jeffrey Weener, Seth Copen Goldstein, Herman Schmit, Donald E. Thomas
1998	A	`conf`	Memory modeling for system synthesis. ISLPED Sari L. Coumeri, Donald E. Thomas
1997	J	`jnl`	Synthesis of application-specific memory designs. IEEE Trans. Very Large Scale Integr. Syst. Herman Schmit, Donald E. Thomas
1996	A*	`conf`	The Design of Mixed Hardware/Software Systems. DAC Jay K. Adams, Donald E. Thomas
1996	—	`book`	The Verilog hardware description language (3. ed.). Donald E. Thomas, Philip Moorby
1995	A	`conf`	Address generation for memories containing multiple arrays. ICCAD Herman Schmit, Donald E. Thomas
1995	—	`conf`	Array mapping in behavioral synthesis. ISSS Herman Schmit, Donald E. Thomas
1995	C	`conf`	Execution-time profiling for multiple-process behavioral synthesis. ICCD Jay K. Adams, John Alan Miller, Donald E. Thomas
1995	Misc	`conf`	Hidden Markov modeling and fuzzy controllers in FPGAs. FCCM Herman Schmit, Donald E. Thomas
1995	A*	`conf`	Multi-way Partitioning for Minimum Delay for Look-Up Table Based FPGAs. DAC Prashant Sawkar, Donald E. Thomas
1995	—	`conf`	Multiple-process behavioral synthesis for mixed hardware-software systems. ISSS Jay K. Adams, Donald E. Thomas
1995	—	`book`	The Verilog hardware description language (2. ed.). Donald E. Thomas, Philip Moorby
1994	—	`conf`	Applications of attributed-behavior synthesis. HLSS Lawrence F. Arnstein, Donald E. Thomas
1994	A	`conf`	Behavioral-Test Generation using Mixed-Integer Non-linear Programming. ITC R. S. Ramchandani, Donald E. Thomas
1994	J	`jnl`	Exploiting the special structure of conflict and compatibility graphs in high-level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. D. L. Springer, Donald E. Thomas
1994	A*	`conf`	The Attributed-Behavior Abstraction and Synthesis Tools. DAC Lawrence F. Arnstein, Donald E. Thomas
1993	J	`jnl`	A Model and Methodology for Hardware-Software Codesign. IEEE Des. Test Comput. Donald E. Thomas, Jay K. Adams, Herman Schmit
1993	J	`jnl`	A dynamic approach to controlling high-level synthesis CAD tools. IEEE Trans. Very Large Scale Integr. Syst. Anthony J. Gadient, Donald E. Thomas
1993	A	`conf`	A general consistency technique for increasing the controllability of high level synthesis tools. ICCAD Lawrence F. Arnstein, Donald E. Thomas
1993	A*	`conf`	Performance Directed Technology Mapping for Look-Up Table Based FPGAs. DAC Prashant Sawkar, Donald E. Thomas
1993	A*	`conf`	Synthesis of Pipelined Instruction Set Processors. DAC Richard J. Cloutier, Donald E. Thomas
1992	C	`conf`	Addressing the Tradeoff Between Standard and Custom ICs in System Level Design. ICCD Jay K. Adams, Donald E. Thomas
1992	A*	`conf`	Area and Delay Mapping for Table-Look-Up Based Field Programmable Gate Arrays. DAC Prashant Sawkar, Donald E. Thomas
1991	J	`jnl`	Architectural partitioning for system level synthesis of integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Elizabeth D. Lagnese, Donald E. Thomas
1991	J	`jnl`	New methods for coloring and clique partitioning in data path allocation. Integr. David Springer, Donald E. Thomas
1990	A	`conf`	Exploiting the Special Structure of Conflict and Compatibility Graphs in High-Level Synthesis. ICCAD D. L. Springer, Donald E. Thomas
1990	A*	`conf`	The Combination of Scheduling, Allocation, and Mapping in a Single Algorithm. DAC Richard J. Cloutier, Donald E. Thomas
1989	A*	`conf`	Architectural Partitioning for System Level Design. DAC Elizabeth D. Lagnese, Donald E. Thomas
1989	J	`jnl`	Behavioral transformation for algorithmic level IC design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Robert A. Walker, Donald E. Thomas
1989	A*	`ed.`	Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989. DAC Donald E. Thomas
1988	A*	`conf`	CORAL II: Linking Behavior and Structure in an IC Design System. DAC Robert L. Blackburn, Donald E. Thomas, Patti M. Koenig
1988	A*	`conf`	The System Architect's Workbench. DAC Donald E. Thomas, Elizabeth M. Dirkes, Robert A. Walker, Jayanth V. Rajan, John A. Nestor, Robert L. Blackburn
1987	J	`jnl`	Linking the Behavioral and Structural Domains of Representation for Digital System Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Donald E. Thomas, Robert L. Blackburn, Jayanth V. Rajan
1985	A*	`conf`	A model of design representation and synthesis. DAC Robert A. Walker, Donald E. Thomas
1985	A*	`conf`	Linking the behavioral and structural dominis of representation in a synthesis system. DAC Robert L. Blackburn, Donald E. Thomas
1985	—	`conf`	Observations on comparing digital systems synthesis techniques. ACM Conference on Computer Science Donald E. Thomas
1985	A*	`conf`	Synthesis by delayed binding of decisions. DAC Jayanth V. Rajan, Donald E. Thomas
1985	A*	`conf`	The VLSI design automation assistant: what's in a knowledge base. DAC Thaddeus J. Kowalski, Donald E. Thomas
1984	J	`jnl`	Probing the State of the Art. IEEE Des. Test Richard M. Sedmak, Donald E. Thomas
1984	J	`jnl`	The VLSI Design Automation Assistant: An IBM System/370 Design. IEEE Des. Test Thaddeus J. Kowalski, Donald E. Thomas
1983	A*	`conf`	A method of automatic data path synthesis. DAC Charles Y. Hitchcock III, Donald E. Thomas
1983	J	`jnl`	Automatic Data Path Synthesis. Computer Donald E. Thomas, Charles Y. Hitchcock III, Thaddeus J. Kowalski, Jayanth V. Rajan, Robert A. Walker
1983	J	`jnl`	Automating Technology Relative Logic Synthesis and Module Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Donald E. Thomas, Gary W. Leive
1983	A*	`conf`	Behavioral level transformation in the CMU-DA system. DAC Robert A. Walker, Donald E. Thomas
1983	J	`jnl`	Defining and Implementing a Multilevel Design Representation with Simulation Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Donald E. Thomas, John A. Nestor
1983	A*	`conf`	The VLSI Design Automation Assistant: Prototype system. DAC Thaddeus J. Kowalski, Donald E. Thomas
1982	A*	`conf`	Defining and implementing a multilevel design representation with simulation applications. DAC John A. Nestor, Donald E. Thomas
1981	A*	`conf`	A technology relative Logic Synthesis and Module Selection system. DAC Gary W. Leive, Donald E. Thomas
1981	J	`jnl`	Measuring Designer Performance to Verify Design Automation Systems. IEEE Trans. Computers Donald E. Thomas, Daniel P. Siewiorek
1979	A*	`conf`	The CMU design automation system: An example of automated data path design. DAC Alice C. Parker, Donald E. Thomas, Daniel P. Siewiorek, Mario Barbacci, Louis J. Hafer, Gary W. Leive, Jinchoon Kim
1978	A*	`conf`	A technology-relative computer-aided design system: Abstract representations, transformations, and design tradeoffs. DAC Edward A. Snow, Daniel P. Siewiorek, Donald E. Thomas
1978	J	`jnl`	The Use of LSI Modules in Computer Structures: Trends and Limitations. Computer Daniel P. Siewiorek, Donald E. Thomas, Don L. Scharfetter
1977	A*	`conf`	Measuring designer performance to verify design automation systems. DAC Donald E. Thomas, Daniel P. Siewiorek