Dominik Sisejkovic

53 papers A* 2A 3B 1C 6Misc 3Journal 24Unranked 13

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	It's Getting Hot in Here: Hardware Security Implications of Thermal Crosstalk on ReRAMs. IEEE Trans. Reliab. Felix Staudigl, Hazem Al Indari, Daniel Schön, Hsin-Yu Chen, Dominik Sisejkovic, Jan Moritz Joseph, Vikas Rana, Stephan Menzel, Amelie Hagelauer, Rainer Leupers
2024	J	`jnl`	QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL. CoRR Lennart M. Reimann, Anschul Prashar, Chiara Ghinami, Rebecca Pelke, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers
2023	J	`jnl`	A survey of contemporary open-source honeypots, frameworks, and tools. J. Netw. Comput. Appl. Niclas Ilg, Paul Duplys, Dominik Sisejkovic, Michael Menth
2023	—	`conf`	AutoLock: Automatic Design of Logic Locking with Evolutionary Computation. DSN-S Zeng Wang, Lilas Alrahis, Dominik Sisejkovic, Ozgur Sinanoglu
2023	J	`jnl`	AutoLock: Automatic Design of Logic Locking with Evolutionary Computation. CoRR Zeng Wang, Lilas Alrahis, Dominik Sisejkovic, Ozgur Sinanoglu
2023	C	`conf`	DeepAttack: A Deep Learning Based Oracle-less Attack on Logic Locking. ISCAS Anand Raj, Nikhitha Avula, Pabitra Das, Dominik Sisejkovic, Farhad Merchant, Amit Acharyya
2023	A*	`conf`	Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware. DAC Felix Staudigl, Thorben Fetz, Rebecca Pelke, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Bolzani Pöhls, Rainer Leupers
2023	J	`jnl`	Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware. CoRR Felix Staudigl, Thorben Fetz, Rebecca Pelke, Dominik Sisejkovic, Jan Moritz Joseph, Leticia Bolzani Poehls, Rainer Leupers
2023	—	`conf`	Gate Camouflaging Using Reconfigurable ISFET-Based Threshold Voltage Defined Logic. NEWCAS Elmira Moussavi, Animesh Singh, Dominik Sisejkovic, Aravind Padma Kumar, Daniyar Kizatov, Sven Ingebrandt, Rainer Leupers, Vivek Pachauri, Farhad Merchant
2023	J	`jnl`	Gate Camouflaging Using Reconfigurable ISFET-Based Threshold Voltage Defined Logic. CoRR Elmira Moussavi, Animesh Singh, Dominik Sisejkovic, Aravind Padma Kumar, Daniyar Kizatov, Sven Ingebrandt, Rainer Leupers, Vivek Pachauri, Farhad Merchant
2023	—	`conf`	Invited Paper: A Holistic Fault Injection Platform for Neuromorphic Hardware. LATS Felix Staudigl, Thorben Fetz, Rebecca Pelke, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Veiras Bolzani Poehls, Rainer Leupers
2023	—	`conf`	Quantitative Information Flow for Hardware: Advancing the Attack Landscape. LASCAS Lennart M. Reimann, Sarp Erdönmez, Dominik Sisejkovic, Rainer Leupers
2023	C	`conf`	SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors. VLSI-SoC Lennart M. Reimann, Jonathan Wiesner, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers
2023	J	`jnl`	SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors. CoRR Lennart M. Reimann, Jonathan Wiesner, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers
2023	Misc	`conf`	Work-in-Progress: A Universal Instrumentation Platform for Non-Volatile Memories. CODES+ISSS Felix Staudigl, Mohammed Hossein, Tobias Ziegler, Hazem Al Indari, Rebecca Pelke, Sebastian Siegel, Dirk J. Wouters, Dominik Sisejkovic, Jan Moritz Joseph, Rainer Leupers
2023	J	`jnl`	Work-in-Progress: A Universal Instrumentation Platform for Non-Volatile Memories. CoRR Felix Staudigl, Mohammed Hossein, Tobias Ziegler, Hazem Al Indari, Rebecca Pelke, Sebastian Siegel, Dirk J. Wouters, Dominik Sisejkovic, Jan Moritz Joseph, Rainer Leupers
2022	—	`conf`	A Temperature Independent Readout Circuit for ISFET-Based Sensor Applications. LATS Elmira Moussavi, Dominik Sisejkovic, Animesh Singh, Daniyar Kizatov, Rainer Leupers, Sven Ingebrandt, Vivek Pachauri, Farhad Merchant
2022	J	`jnl`	A Temperature Independent Readout Circuit for ISFET-Based Sensor Applications. CoRR Elmira Moussavi, Dominik Sisejkovic, Animesh Singh, Daniyar Kizatov, Rainer Leupers, Sven Ingebrandt, Vivek Pachauri, Farhad Merchant
2022	J	`jnl`	Deceptive Logic Locking for Hardware Integrity Protection Against Machine Learning Attacks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers
2022	J	`jnl`	Designing ML-Resilient Locking at Register-Transfer Level. CoRR Dominik Sisejkovic, Luca Collini, Benjamin Tan, Christian Pilato, Ramesh Karri, Rainer Leupers
2022	A*	`conf`	Designing ML-resilient locking at register-transfer level. DAC Dominik Sisejkovic, Luca Collini, Benjamin Tan, Christian Pilato, Ramesh Karri, Rainer Leupers
2022	—	`—`	Designing trustworthy hardware with logic locking. Dominik Sisejkovic
2022	A	`conf`	NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories. DATE Felix Staudigl, Hazem Al Indari, Daniel Schön, Dominik Sisejkovic, Farhad Merchant, Jan Moritz Joseph, Vikas Rana, Stephan Menzel, Rainer Leupers
2022	J	`jnl`	Quantitative Information Flow for Hardware: Advancing the Attack Landscape. CoRR Lennart M. Reimann, Sarp Erdönmez, Dominik Sisejkovic, Rainer Leupers
2022	—	`conf`	X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation. AICAS Felix Staudigl, Karl J. X. Sturm, Maximilian Bartel, Thorben Fetz, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Bolzani Pöhls, Rainer Leupers
2022	J	`jnl`	X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation. CoRR Felix Staudigl, Karl J. X. Sturm, Maximilian Bartel, Thorben Fetz, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Bolzani Pöhls, Rainer Leupers
2022	—	`conf`	pHGen: A pH-Based Key Generation Mechanism Using ISFETs. HOST Elmira Moussavi, Dominik Sisejkovic, Fabian Brings, Daniyar Kizatov, Animesh Singh, Xuan Thang Vu, Rainer Leupers, Sven Ingebrandt, Vivek Pachauri, Farhad Merchant
2022	J	`jnl`	pHGen: A pH-Based Key Generation Mechanism Using ISFETs. CoRR Elmira Moussavi, Dominik Sisejkovic, Fabian Brings, Daniyar Kizatov, Animesh Singh, Xuan Thang Vu, Sven Ingebrandt, Rainer Leupers, Vivek Pachauri, Farhad Merchant
2021	Misc	`conf`	ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework. VLSID Farhad Merchant, Dominik Sisejkovic, Lennart M. Reimann, Kirthihan Yasotharan, Thomas Grass, Rainer Leupers
2021	J	`jnl`	ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework. CoRR Farhad Merchant, Dominik Sisejkovic, Lennart M. Reimann, Kirthihan Yasotharan, Thomas Grass, Rainer Leupers
2021	J	`jnl`	Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach. ACM J. Emerg. Technol. Comput. Syst. Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Harshit Srivastava, Ahmed Hallawa, Rainer Leupers
2021	J	`jnl`	Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attacks. CoRR Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers
2021	C	`conf`	Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities. VLSI-SoC Dominik Sisejkovic, Lennart M. Reimann, Elmira Moussavi, Farhad Merchant, Rainer Leupers
2021	J	`jnl`	Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities. CoRR Dominik Sisejkovic, Lennart M. Reimann, Elmira Moussavi, Farhad Merchant, Rainer Leupers
2021	J	`jnl`	NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories. CoRR Felix Staudigl, Hazem Al Indari, Daniel Schön, Dominik Sisejkovic, Farhad Merchant, Jan Moritz Joseph, Vikas Rana, Stephan Menzel, Rainer Leupers
2021	C	`conf`	QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog. ICCD Lennart M. Reimann, Luca Hanel, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers
2021	J	`jnl`	QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog. CoRR Lennart M. Reimann, Luca Hanel, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers
2021	C	`conf`	Trustworthy Hardware Design with Logic Locking. VLSI-SoC Dominik Sisejkovic, Rainer Leupers
2021	A	`conf`	Vertical IP Protection of the Next-Generation Devices: Quo Vadis? DATE Shubham Rai, Siddharth Garg, Christian Pilato, Vladimir Herdt, Elmira Moussavi, Dominik Sisejkovic, Ramesh Karri, Rolf Drechsler, Farhad Merchant, Akash Kumar
2020	C	`conf`	A secure hardware-software solution based on RISC-V, logic locking and microkernel. SCOPES Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers, Massimiliano Giacometti, Sascha Kegreiß
2020	J	`jnl`	Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach. CoRR Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Harshit Srivastava, Ahmed Hallawa, Rainer Leupers
2020	—	`conf`	Scaling Logic Locking Schemes to Multi-module Hardware Designs. ARCS Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers, Sascha Kegreiß
2019	—	`conf`	A Critical Evaluation of the Paradigm Shift in the Design of Logic Encryption Algorithms. VLSI-DAT Dominik Sisejkovic, Farhad Merchant, Rainer Leupers, Gerd Ascheid, Volker Kiefer
2019	—	`conf`	Control-Lock: Securing Processor Cores Against Software-Controlled Hardware Trojans. ACM Great Lakes Symposium on VLSI Dominik Sisejkovic, Farhad Merchant, Rainer Leupers, Gerd Ascheid, Sascha Kegreiss
2019	B	`conf`	Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries. ETS Dominik Sisejkovic, Farhad Merchant, Rainer Leupers, Gerd Ascheid, Sascha Kegreiss
2019	—	`conf`	Protecting the Integrity of Processor Cores with Logic Encryption. SoCC Dominik Sisejkovic, Farhad Merchant, Rainer Leupers
2018	—	`conf`	A Unifying logic encryption security metric. SAMOS Dominik Sisejkovic, Rainer Leupers, Gerd Ascheid, Simon Metzner
2018	J	`jnl`	Evolving priority rules for resource constrained project scheduling problem with genetic programming. Future Gener. Comput. Syst. Mateja Dumic, Dominik Sisejkovic, Rebeka Coric, Domagoj Jakobovic
2017	J	`jnl`	Immunological algorithms paradigm for construction of Boolean functions with good cryptographic properties. Eng. Appl. Artif. Intell. Stjepan Picek, Dominik Sisejkovic, Domagoj Jakobovic
2016	A	`conf`	Evolving Cryptographic Pseudorandom Number Generators. PPSN Stjepan Picek, Dominik Sisejkovic, Vladimir Rozic, Bohan Yang, Domagoj Jakobovic, Nele Mentens
2016	—	`conf`	Extreme Pipelining Towards the Best Area-Performance Trade-Off in Hardware. AFRICACRYPT Stjepan Picek, Dominik Sisejkovic, Domagoj Jakobovic, Lejla Batina, Bohan Yang, Danilo Sijacic, Nele Mentens
2014	Misc	`conf`	S-box Pipelining Using Genetic Algorithms for High-Throughput AES Implementations: How Fast Can We Go? INDOCRYPT Lejla Batina, Domagoj Jakobovic, Nele Mentens, Stjepan Picek, Antonio de la Piedra, Dominik Sisejkovic
2014	J	`jnl`	S-box pipelining using genetic algorithms for high-throughput AES implementations: How fast can we go? IACR Cryptol. ePrint Arch. Lejla Batina, Domagoj Jakobovic, Nele Mentens, Stjepan Picek, Antonio de la Piedra, Dominik Sisejkovic