Dmitrij Kissler

16 papers B 1C 1Journal 4Unranked 9

Year	Rank	Type	Title / Venue / Authors
2012	—	`—`	Power-Efficient Tightly-Coupled Processor Arrays for Digital Signal Processing. Dmitrij Kissler
2011	J	`jnl`	Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor Arrays. J. Low Power Electron. Dmitrij Kissler, Frank Hannig, Jürgen Teich
2011	J	`jnl`	Scalable Many-Domain Power Gating in Coarse-Grained Reconfigurable Processor Arrays. IEEE Embed. Syst. Lett. Dmitrij Kissler, D. Gran, Zoran Salcic, Frank Hannig, Jürgen Teich
2009	J	`jnl`	A holistic approach for tightly coupled reconfigurable parallel processors. Microprocess. Microsystems Hritam Dutta, Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich, Bernard Pottier
2009	J	`jnl`	Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures. J. Low Power Electron. Dmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich
2008	B	`conf`	Coarse-grained reconfiguration. FPL Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner
2008	—	`conf`	Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures. PATMOS Dmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich
2007	—	`conf`	A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation. ERSA Jürgen Teich, Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Dmitrij Kissler, Andrej Stravet
2007	C	`conf`	Efficient event-driven simulation of parallel processor architectures. SCOPES Alexey Kupriyanov, Dmitrij Kissler, Frank Hannig, Jürgen Teich
2007	—	`conf`	Massively Parallel Processor Architectures: A Co-design Approach. ReCoSoC Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier
2007	—	`conf`	Modeling of Interconnection Networks in Massively Parallel Processor Architectures. ARCS Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement
2006	—	`conf`	A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template. ReCoSoC Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich
2006	—	`conf`	A Generic Framework for Rapid Prototyping of System-on-Chip Designs. CDES Dmitrij Kissler, Alexey Kupriyanov, Frank Hannig, Dirk Koch, Jürgen Teich
2006	—	`conf`	A highly parameterizable parallel processor array architecture. FPT Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich
2006	—	`conf`	An Architecture Description Language for Massively Parallel Processor Architectures. MBMV Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Renate Merker
2006	—	`conf`	Hardware Cost Analysis for Weakly Programmable Processor Arrays. SoC Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich