Dmitri Mihhailov

18 papers B 1C 2Journal 3Unranked 12

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Architectural Exploration and Implementation of CERN LHC Trigger Algorithm With FPGA. IEEE Trans. Very Large Scale Integr. Syst. Sergei Devadze, Christine Elizabeth Nielsen, Natalia Cherezova, Dmitri Mihhailov, Peeter Ellervee
2024	—	`conf`	Architectural Solutions for High-Speed Data Processing Demands of CERN LHC Detectors with FPGA and High-Level Synthesis. NorCAS Sergei Devadze, Christine Elizabeth Nielsen, Dmitri Mihhailov, Peeter Ellervee
2024	J	`jnl`	Architectural Solutions for High-Speed Data Processing Demands of CERN LHC Detectors with FPGA and High-Level Synthesis. CoRR Sergei Devadze, Christine Elizabeth Nielsen, Dmitri Mihhailov, Peeter Ellervee
2022	J	`jnl`	HLS-based Optimization of Tau Triggering Algorithm for LHC: a case study. CoRR Natalia Cherezova, Dmitri Mihhailov, Sergei Devadze, Artur Jutman
2013	—	`conf`	Address-based data processing over N-ary trees. EUROCON Valery Sklyarov, Iouliia Skliarova, Margus Kruus, Dmitri Mihhailov, Alexander Sudnitson
2013	—	`conf`	Implementation of address-based data sorting on different FPGA platforms. EWDTS Dmitri Mihhailov, Alexander Sudnitson, Valery Sklyarov, Iouliia Skliarova
2013	—	`conf`	Optimization of address-based data sorting unit with external memory support. CompSysTech Dmitri Mihhailov, Artjem Rjabov, Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson
2012	—	`conf`	Performance evaluation for FPGA-based processing of tree-like structures. ICECS Valery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander Sudnitson
2011	C	`conf`	EEG Analyzer prototype based on FPGA. ISPA Maksim Jenihhin, Maksim Gorev, Vadim Pesonen, Dmitri Mihhailov, Peeter Ellervee, Hiie Hinrikus, Maie Bachmann, Jaanus Lass
2011	C	`conf`	High-performance hardware accelerators for sorting and managing priorities. DDECS Valery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander Sudnitson
2011	B	`conf`	Implementation in FPGA of Address-Based Data Sorting. FPL Valery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander Sudnitson
2011	—	`conf`	Recursion and hierarchy in digital design and prototyping: a case study. CompSysTech Dmitri Mihhailov, Margus Kruus, Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson
2010	—	`conf`	Advanced topics of FSM design using FPGA educational boards and web-based tools. EWDTS Alexander Sudnitson, Dmitri Mihhailov, Margus Kruus
2010	—	`conf`	Application-specific hardware accelerator for implementing recursive sorting algorithms. FPT Dmitri Mihhailov, Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson
2010	—	`conf`	Parallel FPGA-Based Implementation of Recursive Sorting Algorithms. ReConFig Dmitri Mihhailov, Valery Sklyarov, Iouliia Skliarova, Alexander Sudnitson
2010	—	`conf`	Synthesis and Implementation of Hierarchical Finite State Machines with Implicit Modules. ReConFig Valery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander Sudnitson
2009	—	`conf`	FSM decomposition with application to FPGA synthesis. CompSysTech Alexander Sudnitson, Dmitri Mihhailov, Margus Kruus, Konstantin Tarletski
2008	—	`conf`	FPGA platform based digital design education. CompSysTech Dmitri Mihhailov, Margus Kruus, Alexander Sudnitson