Dirk Koch - RankMe

133 papers A 8B 37C 3Misc 10Journal 17Unranked 49

Year	Rank	Type	Title / Venue / Authors
2025	B	`conf`	Design Space Exploration of Fast RISC-V Processors for Scalable Kilo-Core FPGA Systems. FPL Riadh Ben Abdelhamid, Vladislav Válek, Kevin Klein, Dirk Koch
2025	B	`conf`	FPGAs with FABulous - Framework and Chips. FPL Dirk Koch, Myrtle Shah, King Lok Chung, Jonas Kuenstler, Marcel Jung, Jakob Ternes, Asma Mohsin, Gennadiy Knis
2025	—	`ed.`	Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2025, Kumamoto, Japan, May 26-28, 2025 HEART Tomohiro Ueno, Ameer Abdelhadi, Dirk Koch, Yasunori Osana, Yukinori Sato
2025	B	`conf`	Virtualization and Dynamic Reconfiguration of Custom Instruction Accelerators (CIA) in RISC-V Embedded Systems. FPL Bea Healy, Brandon Freiberger, Jonas Kuenstler, King Lok Chung, Emil Cozac, Meinhard Kissich, Gennadiy Knis, Ron Sass, Dirk Koch, Jan Gray, Guy Lemieux
2024	—	`conf`	Analysis of Process Variation Within Clock Regions of AMD-Xilinx UltraScale+ Devices. ARC Bardia Babaei, Dirk Koch
2024	—	`conf`	BRISKI: A RISC-V barrel processor approach for higher throughput with less resource tax. MCSoC Riadh Ben Abdelhamid, Dirk Koch
2024	—	`conf`	MPD - Multi-Project Die Sharing Enabled by an Embedded FPGA. ICFPT Dirk Koch, Myrtle Shah, Gavaskar Kanagara, Riadh Ben Abdelhamid, Nguyen Dao
2024	Misc	`conf`	Ph.D. Project: ManAge: A Tool for Timing Characterization of FPGAs. FCCM Bardia Babaei, Dirk Koch
2024	—	`conf`	SPARKLE: 400 RISC-V GIPS with 1,024 Barrel Processors on a single Datacenter FPGA Card. MCSoC Riadh Ben Abdelhamid, Vladislav Válek, Dirk Koch
2024	—	`conf`	SPARKLE: A 1,024-Core/16,384-Thread Single FPGA Many-Core RISC-V Barrel Processor Overlay. ASAP Riadh Ben Abdelhamid, Vladislav Válek, Dirk Koch
2023	B	`conf`	Efficient Resource Scheduling for Runtime Reconfigurable Systems on FPGAs. FPL Shaden M. Alismail, Dirk Koch
2023	B	`conf`	FABulous Demo: Open Source FPGA on Sky130. FPL Myrtle Shah, Jakob Ternes, Dirk Koch
2023	—	`conf`	Memory-Aware Scheduling for a Resource-Elastic FPGA Operating System. ARC Shaden M. Alismail, Dirk Koch
2022	—	`conf`	Automated Generation and Orchestration of Stream Processing Pipelines on FPGAs. FPT Kaspar Mätas, Kristiyan Manev, Joseph Powell, Dirk Koch
2022	B	`conf`	FPL Demo: FPGA Bitstream Virus Scanning. FPL Joseph Powell, Kaspar Matas, Kristiyan Manev, Dirk Koch
2022	B	`conf`	FPL Demo: Runtime Stream Processing with Resource-Elastic Pipelines on FPGAs. FPL Kaspar Mätas, Kristiyan Manev, Joseph Powell, Dirk Koch
2022	A	`conf`	How to Shrink My FPGAs - Optimizing Tile Interfaces and the Configuration Logic in FABulous FPGA Fabrics. FPGA King Lok Chung, Nguyen Dao, Jing Yu, Dirk Koch
2022	B	`conf`	Precise Characterizing of FPGAs in Production Systems. FPL Bardia Babaei, Dirk Koch
2022	J	`jnl`	The Future of FPGA Acceleration in Datacenters and the Cloud. ACM Trans. Reconfigurable Technol. Syst. Christophe Bobda, Joel Mandebi Mbongue, Paul Chow, Mohammad Ewais, Naif Tarafdar, Juan Camilo Vega, Ken Eguro, Dirk Koch, Suranga Handagala, Miriam Leeser, Martin C. Herbordt, Hafsah Shahzad, H. Peter Hofstee, Burkhard Ringlein, Jakub Szefer, Ahmed Sanaullah, Russell Tessier
2022	B	`conf`	Tunable Fine-grained Clock Phase-shifting for FPGAs. FPL Bardia Babaei, Dirk Koch
2022	—	`conf`	byteman: A Bitstream Manipulation Framework. FPT Kristiyan Manev, Joseph Powell, Kaspar Matas, Dirk Koch
2021	J	`jnl`	Denial-of-Service on FPGA-based Cloud Infrastructures - Attack and Defense. IACR Trans. Cryptogr. Hardw. Embed. Syst. Tuan La, Khoa Dang Pham, Joseph Powell, Dirk Koch
2021	A	`conf`	FABulous: An Embedded FPGA Framework. FPGA Dirk Koch, Nguyen Dao, Bea Healy, Jing Yu, Andrew Attwood
2021	J	`jnl`	Introduction to the Special Issue on Application-Specific Systems, Architectures and Processors. J. Signal Process. Syst. Frank Hannig, Dirk Koch
2021	C	`conf`	Memristor-Based Pass Gate for FPGA Programmable Routing Switch. ISCAS Nguyen Cong Dao, Dirk Koch
2021	—	`conf`	Memristor-based Pass Gate Targeting FPGA Look-Up Table. ICEIC Nguyen Cong Dao, Dirk Koch
2021	B	`conf`	The FABulous Open eFPGA Ecosystem in Action - From Specifications to Chips to Running Bitsteams. FPL Jing Yu, Andrew Attwood, Nguyen Dao, Dirk Koch
2021	Misc	`conf`	Trusted Configuration in Cloud FPGAs. FCCM Shaza Zeitouni, Jo Vliegen, Tommaso Frassetto, Dirk Koch, Ahmad-Reza Sadeghi, Nele Mentens
2020	B	`conf`	A Self-Compilation Flow Demo on FOS - The FPGA Operating System. FPL Khoa Dang Pham, Anuj Vaishnav, Joseph Powell, Dirk Koch
2020	B	`conf`	Demo: A Closer Look at Malicious Bitstreams. FPL Tuan La, Kaspar Matas, Joseph Powell, Khoa Dang Pham, Dirk Koch
2020	J	`jnl`	Enabling Dynamic System Integration on Maxeler HLS Platforms. J. Signal Process. Syst. Charalampos Kritikakis, Dirk Koch
2020	J	`jnl`	FOS: A Modular FPGA Operating System for Dynamic Workloads. CoRR Anuj Vaishnav, Khoa Dang Pham, Joseph Powell, Dirk Koch
2020	J	`jnl`	FOS: A Modular FPGA Operating System for Dynamic Workloads. ACM Trans. Reconfigurable Technol. Syst. Anuj Vaishnav, Khoa Dang Pham, Joseph Powell, Dirk Koch
2020	J	`jnl`	FPGADefender: Malicious Self-oscillator Scanning for Xilinx UltraScale + FPGAs. ACM Trans. Reconfigurable Technol. Syst. Tuan Minh La, Kaspar Matas, Nikola Grunchevski, Khoa Dang Pham, Dirk Koch
2020	—	`conf`	FlexBex: A RISC-V with a Reconfigurable Instruction Extension. FPT Nguyen Dao, Andrew Attwood, Bea Healy, Dirk Koch
2020	A	`conf`	Invited Tutorial: FPGA Hardware Security for Datacenters and Beyond. FPGA Kaspar Matas, Tuan La, Nikola Grunchevski, Khoa Dang Pham, Dirk Koch
2020	—	`conf`	Message from the Conference Chairs - ASAP 2020. ASAP Dirk Koch, Frank Hannig, Javier Navaridas
2020	—	`conf`	Moving Compute towards Data in Heterogeneous multi-FPGA Clusters using Partial Reconfiguration and I/O Virtualisation. FPT Khoa Dang Pham, Dirk Koch, Anuj Vaishnav, Konstantinos Georgopoulos, Pavlos Malakonakis, Aggelos Ioannou, Iakovos Mavroidis
2020	Misc	`conf`	Power-hammering through Glitch Amplification - Attacks and Mitigation. FCCM Kaspar Matas, Tuan Minh La, Khoa Dang Pham, Dirk Koch
2020	B	`conf`	Resource Elastic Database Acceleration. FPL Kristiyan Manev, Dirk Koch
2020	B	`conf`	Securing FPGA Accelerators at the Electrical Level for Multi-tenant Platforms. FPL Tuan La, Kaspar Matas, Khoa Dang Pham, Dirk Koch
2020	B	`conf`	Transparent Integration of a Dynamic FPGA Database Acceleration System. FPL Kaspar Mätas, Dirk Koch
2019	Misc	`conf`	EFCAD - An Embedded FPGA CAD Tool Flow for Enabling On-chip Self-Compilation. FCCM Khoa Dang Pham, Malte Vesper, Dirk Koch, Eddie Hung
2019	—	`conf`	End-to-end Dynamic Stream Processing on Maxeler HLS Platforms. ASAP Charalampos Kritikakis, Dirk Koch
2019	—	`conf`	Heterogeneous Resource-Elastic Scheduling for CPU+FPGA Architectures. HEART Anuj Vaishnav, Khoa Dang Pham, Dirk Koch
2019	—	`conf`	Scalable Filtering Modules for Database Acceleration on FPGAs. HEART Kristiyan Manev, Anuj Vaishnav, Charalampos Kritikakis, Dirk Koch
2019	B	`conf`	The FOS (FPGA Operating System) Demo. FPL Anuj Vaishnav, Khoa Dang Pham, Kristiyan Manev, Dirk Koch
2019	—	`conf`	Unexpected Diversity: Quantitative Memory Analysis for Zynq UltraScale+ Systems. FPT Kristiyan Manev, Anuj Vaishnav, Dirk Koch
2018	—	`conf`	A Soft Dual-Processor System with a Partially Run-Time Reconfigurable Shared 128-Bit SIMD Engine. ASAP Jose Raul Garcia Ordaz, Dirk Koch
2018	B	`conf`	A Survey on FPGA Virtualization. FPL Anuj Vaishnav, Khoa Dang Pham, Dirk Koch
2018	—	`ed.`	Architecture of Computing Systems - ARCS 2018 - 31st International Conference, Braunschweig, Germany, April 9-12, 2018, Proceedings ARCS Mladen Berekovic, Rainer Buchty, Heiko Hamann, Dirk Koch, Thilo Pionteck
2018	—	`conf`	HLS Enabled Partially Reconfigurable Module Implementation. ARCS Nicolae Bogdan Grigore, Charalampos Kritikakis, Dirk Koch
2018	—	`conf`	IPRDF: An Isolated Partial Reconfiguration Design Flow for Xilinx FPGAs. MCSoC Khoa Dang Pham, Edson L. Horta, Dirk Koch, Anuj Vaishnav, Thomas Kuhn
2018	—	`conf`	Large Utility Sorting on FPGAs. FPT Kristiyan Manev, Dirk Koch
2018	—	`conf`	Live Migration for OpenCL FPGA Accelerators. FPT Anuj Vaishnav, Khoa Dang Pham, Dirk Koch
2018	B	`conf`	Resource Elastic Virtualization for FPGAs Using OpenCL. FPL Anuj Vaishnav, Khoa Dang Pham, Dirk Koch, James D. Garside
2017	B	`conf`	A security library for FPGA interlays. FPL Anuj Vaishnav, Jose Raul Garcia Ordaz, Dirk Koch
2017	B	`conf`	Asynchronous interface FIFO design on FPGA for high-throughput NRZ synchronisation. FPL Gengting Liu, Jim D. Garside, Steve B. Furber, Luis A. Plana, Dirk Koch
2017	A	`conf`	BITMAN: A tool and API for FPGA bitstream manipulations. DATE Khoa Dang Pham, Edson L. Horta, Dirk Koch
2017	—	`conf`	HLS Compilation for CPU Interlays. HEART Jose Raul Garcia Ordaz, Dirk Koch
2017	B	`conf`	Making a case for an ARM Cortex-A9 CPU interlay replacing the NEON SIMD unit. FPL Jose Raul Garcia Ordaz, Dirk Koch
2016	B	`conf`	A partial reconfiguration controller for Altera Stratix V FPGAs. FPL Zhenzhong Xiao, Dirk Koch, Mikel Luján
2016	A	`conf`	ECOSCALE: Reconfigurable computing and runtime system for future exascale systems. DATE Iakovos Mavroidis, Ioannis Papaefstathiou, Luciano Lavagno, Dimitrios S. Nikolopoulos, Dirk Koch, John Goodacre, Ioannis Sourdis, Vassilis Papaefstathiou, Marcello Coppola, Manuel Palomino
2016	—	`ch.`	FPGA Versus Software Programming: Why, When, and How? FPGAs for Software Programmers Dirk Koch, Daniel Ziener, Frank Hannig
2016	—	`book`	FPGAs for Software Programmers Dirk Koch, Frank Hannig, Daniel Ziener
2016	B	`conf`	JetStream: An open-source high-performance PCI Express 3 streaming library for FPGA-to-Host and FPGA-to-FPGA communication. FPL Malte Vesper, Dirk Koch, Kizheppatt Vipin, Suhaib A. Fahmy
2016	Misc	`conf`	Parallel Hardware Merge Sorter. FCCM Wei Song, Dirk Koch, Mikel Luján, Jim D. Garside
2016	—	`conf`	soft-NEON: A study on replacing the NEON engine of an ARM SoC with a reconfigurable fabric. ASAP Jose Raul Garcia Ordaz, Dirk Koch
2015	B	`conf`	Placing partially reconfigurable stream processing applications on FPGAs. FPL Nicolae Bogdan Grigore, Dirk Koch
2015	J	`jnl`	Practical feasibility evaluation and improvement of a pay-per-use licensing scheme for hardware IP cores in Xilinx FPGAs. J. Cryptogr. Eng. Jo Vliegen, Nele Mentens, Dirk Koch, Dries Schellekens, Ingrid Verbauwhede
2015	J	`jnl`	Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP 2015). CoRR Frank Hannig, Dirk Koch, Daniel Ziener
2015	Misc	`conf`	Rapid Overlay Builder for Xilinx FPGAs. FCCM Michael Xi Yue, Dirk Koch, Guy G. F. Lemieux
2014	J	`jnl`	Design Tools for Implementing Self-Aware and Fault-Tolerant Systems on FPGAs. ACM Trans. Reconfigurable Technol. Syst. Christian Beckhoff, Dirk Koch, Jim Tørresen
2014	B	`conf`	Hierarchical reconfiguration of FPGAs. FPL Dirk Koch, Christian Beckhoff
2014	B	`conf`	Portable module relocation and bitstream compression for Xilinx FPGAs. FPL Christian Beckhoff, Dirk Koch, Jim Tørresen
2014	J	`jnl`	Proceedings of the First International Workshop on FPGAs for Software Programmers (FSP 2014). CoRR Frank Hannig, Dirk Koch, Daniel Ziener
2013	B	`conf`	An efficient FPGA overlay for portable custom instruction set extensions. FPL Dirk Koch, Christian Beckhoff, Guy G. F. Lemieux
2013	—	`conf`	Automatic Floorplanning and Interface Synthesis of Island Style Reconfigurable Systems with GoAhead. ARCS Christian Beckhoff, Dirk Koch, Jim Tørresen
2013	B	`conf`	Building partial systems with GoAhead. FPL Christian Beckhoff, Alexander Wold, Anders Fritzell, Dirk Koch, Jim Tørresen
2013	—	`conf`	Component based design using constraint programming for module placement on FPGAs. ReCoSoC Alexander Wold, Dirk Koch, Jim Tørresen
2013	—	`conf`	EasyPR - An easy usable open-source PR system. FPT Dirk Koch, Christian Beckhoff, Alexander Wold, Jim Tørresen
2013	—	`book`	Partial Reconfiguration on FPGAs - Architectures, Tools and Applications Dirk Koch
2013	B	`conf`	Remote FPGA design through eDiViDe - European Digital Virtual Design Lab. FPL Jochen Vandorpe, Jo Vliegen, Ruben Smeets, Nele Mentens, Milos Drutarovský, Michal Varchola, Kerstin Lemke-Rust, Paul Plöger, Peter Samarin, Dirk Koch, Yngve Hafting, Jim Tørresen
2013	—	`conf`	Simulation framework for cycle-accurate RTL modeling of partial run-time reconfiguration in VHDL. ReCoSoC Simen Gimle Hansen, Dirk Koch, Jim Tørresen
2013	—	`conf`	Thermal Aware Module Placement for Heterogeneous 3D-IC Based FPGAs. IPDPS Workshops Alexander Wold, Dirk Koch, Jim Tørresen
2012	B	`ed.`	22nd International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, August 29-31, 2012 FPL Dirk Koch, Satnam Singh, Jim Tørresen
2012	C	`conf`	Design techniques for increasing performance and resource utilization of reconfigurable soft CPUs. DDECS Alexander Wold, Dirk Koch, Jim Tørresen
2012	J	`jnl`	Dynamic Defragmentation of Reconfigurable Devices. ACM Trans. Reconfigurable Technol. Syst. Sándor P. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch, Jürgen Teich
2012	Misc	`conf`	Go Ahead: A Partial Reconfiguration Framework. FCCM Christian Beckhoff, Dirk Koch, Jim Tørresen
2012	—	`conf`	Partial Reconfiguration on FPGAs in Practice - Tools and Applications. ARCS Workshops Dirk Koch, Jim Tørresen, Christian Beckhoff, Daniel Ziener, Christopher Dennl, Volker Breuer, Jürgen Teich, Michael Feilen, Walter Stechele
2011	B	`conf`	A Routing Architecture for Mapping Dataflow Graphs at Run-Time. FPL Dirk Koch, Jim Tørresen
2011	—	`conf`	Enhancing Resource Utilization with Design Alternatives in Runtime Reconfigurable Systems. IPDPS Workshops Alexander Wold, Dirk Koch, Jim Tørresen
2011	A	`conf`	FPGASort: a high performance sorting architecture exploiting run-time reconfiguration on fpgas for large problem sorting. FPGA Dirk Koch, Jim Tørresen
2011	J	`jnl`	Genetic algorithm using a modified backward pass heuristic for the dynamic facility layout problem. Paladyn J. Behav. Robotics Kazi Shah Nawaz Ripon, Kyrre Glette, Dirk Koch, Mats Høvin, Jim Tørresen
2011	—	`conf`	High Speed Partial Run-Time Reconfiguration Using Enhanced ICAP Hard Macro. IPDPS Workshops Simen Gimle Hansen, Dirk Koch, Jim Tørresen
2011	—	`conf`	Migrating Static Systems to Partially Reconfigurable Systems on Spartan-6 FPGAs. IPDPS Workshops Christian Beckhoff, Dirk Koch, Jim Tørresen
2011	—	`conf`	The Xilinx Design Language (XDL): Tutorial and use cases. ReCoSoC Christian Beckhoff, Dirk Koch, Jim Tørresen
2010	B	`conf`	A Bus-Based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs. FPL Andreas Oetken, Stefan Wildermann, Jürgen Teich, Dirk Koch
2010	—	`conf`	A new project to address run-time reconfigurable hardware systems. Dynamically Reconfigurable Architectures Jim Tørresen, Dirk Koch
2010	—	`conf`	Advanced partial run-time reconfiguration on Spartan-6 FPGAs. FPT Dirk Koch, Christian Beckhoff, Jim Tørresen
2010	—	`conf`	Advances in Component-based System Design and Partial Run-time Reconfiguration. Dynamically Reconfigurable Architectures Dirk Koch
2010	Misc	`conf`	Fine-Grained Partial Runtime Reconfiguration on Virtex-5 FPGAs. FCCM Dirk Koch, Christian Beckhoff, Jim Tørresen
2010	J	`jnl`	No-Break Dynamic Defragmentation of Reconfigurable CoRR Sándor P. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch, Jürgen Teich
2010	—	`conf`	Obstacle-free two-dimensional online-routing for run-time reconfigurable FPGA-based systems. FPT Dirk Koch, Christian Beckhoff, Jim Tørresen
2010	—	`ch.`	ReCoNets - Design Methodology for Embedded Systems Consisting of Small Networks of Reconfigurable Nodes and Connections. Dynamically Reconfigurable Systems Christian Haubelt, Dirk Koch, Felix Reimann, Thilo Streichert, Jürgen Teich
2010	—	`ch.`	ReCoNodes - Optimization Methods for Module Scheduling and Placement on Reconfigurable Hardware Devices. Dynamically Reconfigurable Systems Ali Ahmadinia, Josef Angermeier, Sándor P. Fekete, Tom Kamphans, Dirk Koch, Mateusz Majer, Nils Schweer, Jürgen Teich, Christopher Tessars, Jan van der Veen
2010	—	`conf`	Routing optimizations for component-based system design and partial run-time reconfiguration on FPGAs. FPT Dirk Koch, Jim Tørresen
2010	B	`conf`	Short-Circuits on FPGAs Caused by Partial Runtime Reconfiguration. FPL Christian Beckhoff, Dirk Koch, Jim Tørresen
2010	—	`conf`	Zero logic overhead integration of partially reconfigurable modules. SBCCI Dirk Koch, Christian Beckhoff, Jim Tørresen
2009	A	`conf`	A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAs. FPGA Dirk Koch, Christian Beckhoff, Jürgen Teich
2009	—	`—`	Architectures, methods, and tools for distributed run-time reconfigurable FPGA-based systems. Dirk Koch
2009	J	`jnl`	Hardware Decompression Techniques for FPGA-Based Embedded Systems. ACM Trans. Reconfigurable Technol. Syst. Dirk Koch, Christian Beckhoff, Jürgen Teich
2009	Misc	`conf`	Minimizing Internal Fragmentation by Fine-Grained Two-Dimensional Module Placement for Runtime Reconfiguralble Systems. FCCM Dirk Koch, Christian Beckhoff, Jürgen Teich
2008	—	`ch.`	Concepts for Self-Adaptive and Self-Healing Networked Embedded Systems. Organic Computing Thilo Streichert, Christian Haubelt, Dirk Koch, Jürgen Teich
2008	—	`conf`	Dynamic Reconfiguration of FlexRay Schedules for Response Time Reduction in Asynchronous Fault-Tolerant Networks. ARCS Robert Brendle, Thilo Streichert, Dirk Koch, Christian Haubelt, Jürgen Teich
2008	Misc	`conf`	Efficient Reconfigurable On-Chip Buses for FPGAs. FCCM Dirk Koch, Christian Haubelt, Jürgen Teich
2008	B	`conf`	No-break dynamic defragmentation of reconfigurable devices. FPL Sándor P. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch, Jürgen Teich
2008	J	`jnl`	Photo-realistic Rendering of Metallic Car Paint from Image-Based Measurements. Comput. Graph. Forum Martin Rump, Gero Müller, Ralf Sarlette, Dirk Koch, Reinhard Klein
2008	B	`conf`	ReCoBus-Builder - A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS. FPL Dirk Koch, Christian Beckhoff, Jürgen Teich
2007	—	`conf`	Bitstream Decompression for High Speed FPGA Configuration from Slow Memories. FPT Dirk Koch, Christian Beckhoff, Jürgen Teich
2007	A	`conf`	Efficient hardware checkpointing: concepts, overhead analysis, and implementation. FPGA Dirk Koch, Christian Haubelt, Jürgen Teich
2007	C	`conf`	Modeling and Synthesis of Hardware-Software Morphing. ISCAS Dirk Koch, Christian Haubelt, Thilo Streichert, Jürgen Teich
2006	—	`conf`	A Generic Framework for Rapid Prototyping of System-on-Chip Designs. CDES Dmitrij Kissler, Alexey Kupriyanov, Frank Hannig, Dirk Koch, Jürgen Teich
2006	—	`conf`	An Operating System Infrastructure for Fault-Tolerant Reconfigurable Networks. ARCS Dirk Koch, Thilo Streichert, Steffen Dittrich, Christian Strengert, Christian Haubelt, Jürgen Teich
2006	J	`jnl`	Modeling and Design of Fault-Tolerant and Self-Adaptive Reconfigurable Networked Embedded Systems. EURASIP J. Embed. Syst. Thilo Streichert, Dirk Koch, Christian Haubelt, Jürgen Teich
2006	—	`conf`	Searching RC5-Keys with Distributed Reconfigurable Computing. ERSA Dirk Koch, Matthiaas Koerber, Jürgen Teich
2004	B	`conf`	A Dynamic NoC Approach for Communication in Reconfigurable Devices. FPL Christophe Bobda, Mateusz Majer, Dirk Koch, Ali Ahmadinia, Jürgen Teich
2004	—	`conf`	Basic OS Support for Distributed Reconfigurable Hardware. SAMOS Christian Haubelt, Dirk Koch, Jürgen Teich
2004	—	`conf`	FPGA architecture extensions for preemptive multitasking and hardware defragmentation. FPT Dirk Koch, Ali Ahmadinia, Christophe Bobda, Heiko Kalte
2004	—	`conf`	Platform-independent methodology for partial reconfiguration. Conf. Computing Frontiers Dirk Koch, Jürgen Teich
2004	B	`conf`	Preemptive Hardware Task Management. FPL Dirk Koch
2004	—	`conf`	Task scheduling for heterogeneous reconfigurable computers. SBCCI Ali Ahmadinia, Christophe Bobda, Dirk Koch, Mateusz Majer, Jürgen Teich
2003	—	`conf`	ReCoNet: Modeling and Implementation of Fault Tolerant Distributed Reconfigurable Hardware. SBCCI Christian Haubelt, Dirk Koch, Jürgen Teich