Dipankar Sarkar

56 papers B 5C 3Misc 4Journal 25Unranked 19

Year	Rank	Type	Title / Venue / Authors
2022	J	`jnl`	Translation validation of coloured Petri net models of programs on integers. Acta Informatica Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal, Holger Giese
2019	J	`jnl`	Equivalence checking of Petri net models of programs using static and dynamic cut-points. Acta Informatica Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan Mandal
2019	—	`conf`	SamaTulyataOne: A Path Based Equivalence Checker. ISEC Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan Mandal
2019	J	`jnl`	Verification of parallelising transformations of KPN models. IET Cyper-Phys. Syst.: Theory & Appl. Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal
2017	B	`conf`	An Equivalence Checking Framework for Array-Intensive Programs. ATVA Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar
2017	J	`jnl`	Deriving Bisimulation Relations from Path Extension Based Equivalence Checkers. IEEE Trans. Software Eng. Kunal Banerjee, Dipankar Sarkar, Chittaranjan Mandal
2017	J	`jnl`	Deriving bisimulation relations from path based equivalence checkers. Formal Aspects Comput. Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal
2017	B	`conf`	SamaTulyata: An Efficient Path Based Equivalence Checking Tool. ATVA Soumyadip Bandyopadhyay, Santonu Sarkar, Dipankar Sarkar, Chittaranjan A. Mandal
2017	J	`jnl`	Synchronization Validation for Cross-Thread Dependences in Parallel Programs. Int. J. Parallel Program. Sudakshina Dutta, Dipankar Sarkar, Arvind Rawat
2016	J	`jnl`	A Path Construction Algorithm for Translation Validation Using PRES+ Models. Parallel Process. Lett. Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal, Kunal Banerjee, Krishnam Raju Duddu
2016	B	`conf`	An Enhanced Equivalence Checking Method to Handle Bugs in Programs with Recurrences. ENASE Sudakshina Dutta, Dipankar Sarkar
2016	—	`conf`	An efficient path based equivalence checking for Petri net based models of programs. ISEC Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal
2016	B	`conf`	Translation validation of loop and arithmetic transformations in the presence of recurrences. LCTES Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar
2016	B	`conf`	Validation of Loop Parallelization and Loop Vectorization Transformations. ENASE Sudakshina Dutta, Dipankar Sarkar, Arvind Rawat, Kulwant Singh
2015	—	`conf`	A Path-based Equivalence Checking Method for Petri Net based Models of Programs. ICSOFT-EA Soumyadip Bandyopadhyay, Dipankar Sarkar, Kunal Banerjee, Chittaranjan A. Mandal
2015	C	`conf`	A translation validation framework for symbolic value propagation based equivalence checking of FSMDAs. SCAM Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar
2015	—	`conf`	Poster: An Efficient Equivalence Checking Method for Petri Net Based Models of Programs. ICSE (2) Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal
2015	—	`conf`	Translation Validation of Transformations of Embedded System Specifications Using Equivalence Checking. ISVLSI Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar
2015	—	`conf`	Validating SPARK: High Level Synthesis Compiler. ISVLSI Soumyadip Bandyopadhyay, Dipankar Sarkar, Chittaranjan A. Mandal
2014	J	`jnl`	Extending the FSMD Framework for Validating Code Motions of Array-Handling Programs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal
2014	—	`conf`	Extending the scope of translation validation by augmenting path based equivalence checkers with SMT solvers. VDAT Kunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar
2014	J	`jnl`	Verification of Code Motion Techniques Using Value Propagation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kunal Banerjee, Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal
2013	J	`jnl`	A Kleene Algebra of Tagged System Actors for Reasoning about Heterogeneous Embedded Systems. IEEE Trans. Computers Soumyajit Dey, Dipankar Sarkar, Anupam Basu
2013	Misc	`conf`	Verification of KPN Level Transformations. VLSI Design Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal
2013	J	`jnl`	Verification of Loop and Arithmetic Transformations of Array-Intensive Behaviors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chandan Karfa, Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal
2012	—	`conf`	A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques. ISED Kunal Banerjee, Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal
2012	J	`jnl`	Formal verification of code motion techniques using data-flow-driven equivalence checking. ACM Trans. Design Autom. Electr. Syst. Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar
2012	—	`conf`	Translation Validation for PRES+ Models of Parallel Behaviours via an FSMD Equivalence Checker. VDAT Soumyadip Bandyopadhyay, Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal
2011	J	`jnl`	A Kleene Algebra of Tagged System Actors. IEEE Embed. Syst. Lett. Soumyajit Dey, Dipankar Sarkar, Anupam Basu
2011	—	`conf`	Equivalence Checking of Array-Intensive Programs. ISVLSI Chandan Karfa, Kunal Banerjee, Dipankar Sarkar, Chitta Mandal
2011	—	`conf`	Verification of Register Transfer Level Low Power Transformations. ISVLSI Chandan Karfa, Chitta Mandal, Dipankar Sarkar
2010	J	`jnl`	A Tag Machine Based Performance Evaluation Method for Job-Shop Schedules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Soumyajit Dey, Dipankar Sarkar, Anupam Basu
2010	—	`conf`	Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques. ISVLSI Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal
2010	J	`jnl`	Diagnosability of delay-deadline failures in fair real time discrete event models. Int. J. Syst. Sci. Santosh Biswas, Dipankar Sarkar, Siddhartha Mukhopadhyay
2010	J	`jnl`	Fairness of Transitions in Diagnosability of Discrete Event Systems. Discret. Event Dyn. Syst. Santosh Biswas, Dipankar Sarkar, Siddhartha Mukhopadhyay, Amit Patra
2010	J	`jnl`	Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chandan Karfa, Dipankar Sarkar, Chitta Mandal
2008	J	`jnl`	An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chandan Karfa, Dipankar Sarkar, Chitta Mandal, P. Kumar
2008	J	`jnl`	Unified Technique for on-Line Testing of Digital Circuits: Delay and Stuck-at Fault Models. J. Circuits Syst. Comput. Santosh Biswas, Siddhartha Mukhopadhyay, Amit Patra, Dipankar Sarkar
2007	J	`jnl`	Fault diagnosis in discrete time hybrid systems - A case study. Inf. Sci. Prodip Bhowal, Dipankar Sarkar, Siddhartha Mukhopadhyay, Anupam Basu
2007	—	`conf`	Hand-in-hand verification of high-level synthesis. ACM Great Lakes Symposium on VLSI Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal, Chris Reade
2007	—	`conf`	Register Sharing Verification During Data-Path Synthesis. ICCTA Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, Chris Reade
2006	—	`conf`	A Formal Verification Method of Scheduling in High-level Synthesis. ISQED Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade
2006	C	`conf`	Concurrent Testing of Digital Circuits for Advanced Fault Models. DDECS Santosh Biswas, Siddhartha Mukhopadhyay, P. Patra, Dipankar Sarkar
2006	C	`conf`	Fairness of transitions in diagnosability analysis of hybrid systems. ACC Santosh Biswas, Chandan Karfa, Himani Kanwar, Dipankar Sarkar, Siddhartha Mukhopadhyay, Amit Patra
2006	—	`conf`	Verification of Scheduling in High-level Synthesis. ISVLSI Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade
2005	—	`conf`	On-Line Testing of Digital Circuits for n-Detect and Bridging Fault Models. Asian Test Symposium Santosh Biswas, P. Srikanth, R. Jha, Siddhartha Mukhopadhyay, Amit Patra, Dipankar Sarkar
2004	—	`conf`	Model checking on state transition diagram. ASP-DAC Batsayan Das, Dipankar Sarkar, Santanu Chattopadhyay
2002	—	`conf`	Register Transfer Operation Analysis during Data Path Verification. ASP-DAC/VLSI Design Dipankar Sarkar
2000	Misc	`conf`	Status Condition Analysis during Data Path Verification of Sequential Circuits. VLSI Design Dipankar Sarkar
1997	Misc	`conf`	Inductive Verification of Sequential Circuits with a Datapath. VLSI Design I. Chakrabarti, Dipankar Sarkar, Arun K. Majumdar
1997	J	`jnl`	Verification of Tempura specification of sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. M. Hira, Dipankar Sarkar
1995	J	`jnl`	Identification of Inductive Properties during Verification of Synchronous Sequential Circuits. J. Autom. Reason. I. Chakrabarti, Dipankar Sarkar, Arun K. Majumdar
1994	Misc	`conf`	Mechanical Identification of Inductive Properties During Verification of Finite State Machines. VLSI Design I. Chakrabarti, Dipankar Sarkar
1989	J	`jnl`	A Set of Inference Rules for Quantified Formula Handling and Array Handling in Verification of Programs Over Integers. IEEE Trans. Software Eng. Dipankar Sarkar, S. C. De Sarkar
1989	J	`jnl`	A Theorem Prover for Verifying Iterative Programs Over Integers. IEEE Trans. Software Eng. Dipankar Sarkar, S. C. De Sarkar
1989	J	`jnl`	Some Inference Rules for Integer Arithmetic for Verification of Flowchart Programs on Integers. IEEE Trans. Software Eng. Dipankar Sarkar, S. C. De Sarkar