Dipankar Pal

22 papers A 1C 5Misc 1Journal 6Unranked 9
YearRankTypeTitle / Venue / Authors
2025 — conf
Interactive Transaction Tracker to Validate Data Integrity of the Compression and Decompression Engines in Neural Camera Applications.
SOCC
Surajit Bhattacherjee, Dipankar Pal
2024 — conf
Deploying Artificial Intelligence in Design Verification to Accelerate IP/SoC Sign-off with Zero Escape.
AICAS
Surajit Bhattacherjee, Daksh Shah, Dipankar Pal
2024 J jnl
Strong-ARM Dynamic Latch Comparators: Design and Analyses on CAD Platform.
CoRR
Kasi Bandla, Dipankar Pal
2023 Misc conf
IP Transformation Initiatives to Generate Scalable Functional Verification Collaterals for Smart Reusability and Reduced Effort for Sign-off.
ICNC
Surajit Bhattacherjee, Dipankar Pal
2022 J jnl
Pair-Wise Urdhava-Tiryagbhyam (UT) Vedic Ternary multiplier.
Microelectron. J.
Aloke Saha, Rakesh Kumar Singh, Dipankar Pal
2021 J jnl
Efficient ternary comparator on CMOS technology.
Microelectron. J.
Aloke Saha, Narendra Deo Singh, Dipankar Pal
2021 C conf
Novel All-Pass Section for High-Performance Signal Processing Using CMOS DCCII.
TENCON
Taaha Nizam, Vallabhuni Vijay, Avireni Srinivasulu, Dipankar Pal
2020 — conf
ASIC Implementation of High-Speed Adaptive Recursive Karatsuba Multiplier with Square-Root-Carry-Select-Adder.
LASCAS
Akhilesh G. Naik, Debarshi Deka, Dipankar Pal
2019 C conf
RF Harvesting System for Low-Power Applications Using FinFETs.
ICCE
T. Nagateja, Avireni Srinivasulu, Dipankar Pal
2018 — conf
Delay estimation, chip-power analyses and comparison of single-level and multi-level recursive vedic algorithm with conventional algorithms for digital multiplier.
ICICDT
Dipankar Pal, Akhilesh G. Naik
2018 C conf
Modified Time-Based Current Mode ADC.
TENCON
Suparno Pal, Dipankar Pal
2018 J jnl
Secured and Imperceptible Data Transmission Through Digital Audio Signal with Reduced Internal Noise.
Wirel. Pers. Commun.
Dipankar Pal, Nabin Ghoshal
2017 A conf
CCII+ based dual square-and-triangular waveform generator.
ECAI
Avireni Srinivasulu, Dipankar Pal
2014 — conf
A Low Power 8-Bit Asynchronous SAR ADC Design Using Charge Scaling DAC.
ISED
Anush Bekal, Manish Goswami, B. R. Singh, Dipankar Pal
2013 J jnl
Low-power 6-GHz wave-pipelined 8b x 8b multiplier.
IET Circuits Devices Syst.
Aloke Saha, Dipankar Pal, Mahesh Chandra
2010 C conf
A wide-input linear range sub-threshold transconductor for sub-Hz filtering.
ISCAS
Chutham Sawigun, Dipankar Pal, Andreas Demosthenous
2009 J jnl
Current Conveyor-Based Square/Triangular Waveform Generators With Improved Linearity.
IEEE Trans. Instrum. Meas.
Dipankar Pal, Avireni Srinivasulu, Basab Bijoy Pal, Andreas Demosthenous, B. N. Das
2009 C conf
Novel Current-mode Waveform Generator with Independent Frequency and Amplitude Control.
ISCAS
Dipankar Pal, Avireni Srinivasulu, Manish Goswami
2007 — conf
A low-power CMOS analog voltage buffer using compact adaptive biasing.
ECCTD
Chutham Sawigun, Jirayuth Mahattanakul, Andreas Demosthenous, Dipankar Pal
2007 — conf
A low-voltage, low-power, high-linearity cmos four-quadrant analog multiplier.
ECCTD
Chutham Sawigun, Andreas Demosthenous, Dipankar Pal
2005 — conf
10-channel very low noise ENG amplifier system using CMOS technology.
ISCAS (1)
Robert Rieger, Dipankar Pal, John Taylor, Chris Clarke, Peter J. Langlois, Nick Donaldson
2005 — conf
Two preamplifiers for non-invasive on-chip recording of neural-signals.
ISCAS (3)
Robert Rieger, Dipankar Pal, John Taylor, Peter J. Langlois