Ding-Ming Kwai

83 papers A* 2A 3B 3C 2Misc 6Journal 29Unranked 38

Year	Rank	Type	Title / Venue / Authors
2020	—	`conf`	Refresh Power Reduction of DRAMs in DNN Systems Using Hybrid Voting and ECC Method. ITC-Asia Tsung-Fu Hsieh, Jin-Fu Li, Jenn-Shiang Lai, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou
2020	J	`jnl`	Time-to-Digital Converter Compiler for On-Chip Instrumentation. IEEE Des. Test Chia-Hua Wu, Shi-Yu Huang, Yung-Fa Chou, Ding-Ming Kwai
2018	—	`conf`	A channel-sharable built-in self-test scheme for multi-channel DRAMs. ASP-DAC Kuan-Te Wu, Jin-Fu Li, Chih-Yen Lo, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou
2017	—	`conf`	23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache. ISSCC Tah-Kang Joseph Ting, Gyh-Bin Wang, Ming-Hung Wang, Chun-Peng Wu, Chun-Kai Wang, Chun-Wei Lo, Li-Chin Tien, Der-Min Yuan, Yung-Ching Hsieh, Jenn-Shiang Lai, Wen-Pin Hsu, Chien-Chih Huang, Chi-Kang Chen, Yung-Fa Chou, Ding-Ming Kwai, Zhe Wang, Wei Wu, Shigeki Tomishima, Patrick Stolt, Shih-Lien Lu
2017	C	`conf`	DLL-Assisted Clock Synchronization Method for Multi-Die ICs. ICCD Chia-Yuan Cheng, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou
2017	—	`conf`	Heterogeneous chip power delivery modeling and co-synthesis for practical 3DIC realization. ASP-DAC Wei-Hsun Liao, Chang-Tzu Lin, Sheng-Hsin Fang, Chien-Chia Huang, Hung-Ming Chen, Ding-Ming Kwai, Yung-Fa Chou
2017	—	`conf`	On Tolerating Faults of TSV/Microbumps for Power Delivery Networks in 3D IC. ISVLSI Sheng-Hsin Fang, Chang-Tzu Lin, Wei-Hsun Liao, Chien-Chia Huang, Li-Chin Chen, Hung-Ming Chen, I-Hsuan Lee, Ding-Ming Kwai, Yung-Fa Chou
2017	—	`conf`	Resilient Cell-Based Architecture for Time-to-Digital Converter. ISVLSI Chia-Hua Wu, Shi-Yu Huang, Mason Chern, Yung-Fa Chou, Ding-Ming Kwai
2017	—	`conf`	Software-hardware-cooperated built-in self-test scheme for channel-based DRAMs. ITC-Asia Tsung-Fu Hsieh, Jin-Fu Li, Kuan-Te Wu, Jenn-Shiang Lai, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou
2016	—	`conf`	A Test Method for Finding Boundary Currents of 1T1R Memristor Memories. ATS Tzu-Ying Lin, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou
2016	A	`conf`	A built-in self-repair scheme for DRAMs with spare rows, columns, and bits. ITC Chih-Sheng Hou, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou
2015	—	`conf`	A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs. VLSIC Pei-Wen Luo, Chi-Kang Chen, Yu-Hui Sung, Wei Wu, Hsiu-Chuan Shih, Chia-Hsin Lee, Kuo-Hua Lee, Ming-Wei Li, Mei-Chiang Lung, Chun-Nan Lu, Yung-Fa Chou, Po-Lin Shih, Chung-Hu Ke, Chun Shiah, Patrick Stolt, Shigeki Tomishima, Ding-Ming Kwai, Bor-Doou Rong, Nicky Lu, Shih-Lien Lu, Cheng-Wen Wu
2015	—	`conf`	A hybrid built-in self-test scheme for DRAMs. VLSI-DAT Chi-Chun Yang, Jin-Fu Li, Yun-Chao Yu, Kuan-Te Wu, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou
2015	J	`jnl`	Hierarchical Test Integration Methodology for 3-D ICs. IEEE Des. Test Che-Wei Chou, Jin-Fu Li, Yun-Chao Yu, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou
2015	—	`conf`	Temperature-aware online testing of power-delivery TSVs. 3DIC Hua-Cheng Fu, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou
2014	—	`conf`	A power delivery network (PDN) engineering change order (ECO) approach for repairing IR-drop failures after the routing stage. VLSI-DAT Tsu-Wei Tseng, Chang-Tzu Lin, Chia-Hsin Lee, Yung-Fa Chou, Ding-Ming Kwai
2014	J	`jnl`	Application-Independent Testing of 3-D Field Programmable Gate Array Interconnect Faults. IEEE Trans. Very Large Scale Integr. Syst. Yen-Lin Peng, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
2014	—	`conf`	BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs. ATS Yun-Chao You, Chi-Chun Yang, Jin-Fu Li, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
2014	J	`jnl`	DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hsiu-Chuan Shih, Pei-Wen Luo, Jen-Chieh Yeh, Shu-Yen Lin, Ding-Ming Kwai, Shih-Lien Lu, Andre Schaefer, Cheng-Wen Wu
2014	C	`conf`	Improving power delivery network design by practical methodologies. ICCD Chia-Chi Huang, Chang-Tzu Lin, Wei-Syun Liao, Chieh-Jui Lee, Hung-Ming Chen, Chia-Hsin Lee, Ding-Ming Kwai
2014	—	`conf`	Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs. ATS Kuan-Te Wu, Jin-Fu Li, Yun-Chao Yu, Chih-Sheng Hou, Chi-Chun Yang, Ding-Ming Kwai, Yung-Fa Chou, Chih-Yen Lo
2014	J	`jnl`	Thermal-Aware On-Line Scheduler for 3-D Many-Core Processor Throughput Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cody Hao Yu, Chiao-Ling Lung, Yi-Lun Ho, Ruei-Siang Hsu, Ding-Ming Kwai, Shih-Chieh Chang
2013	—	`conf`	A case study: 3-D stacked memory system architecture exploration by ESL virtual platform. VLSI-DAT Hsien-Ching Hsieh, Shr-Je Lin, Chun-Nan Liu, Jen-Chieh Yeh, Shing-Wu Tung, Ding-Ming Kwai
2013	Misc	`conf`	A hybrid ECC and redundancy technique for reducing refresh power of DRAMs. VTS Yun-Chao You, Chih-Sheng Hou, Li-Jung Chang, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
2013	—	`conf`	An FPGA-based test platform for analyzing data retention time distribution of DRAMs. VLSI-DAT Chih-Sheng Hou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
2013	—	`conf`	Benchmarking for research in power delivery networks of three-dimensional integrated circuits. ISPD Pei-Wen Luo, Chun Zhang, Yung-Tai Chang, Liang-Chia Cheng, Hung-Hsie Lee, Bih-Lan Sheu, Yu-Shih Su, Ding-Ming Kwai, Yiyu Shi
2013	J	`jnl`	Die-to-Die Clock Synchronization for 3-D IC Using Dual Locking Mechanism. IEEE Trans. Circuits Syst. I Regul. Pap. Ji-Wei Ker, Shi-Yu Huang, Chao-Wen Tzeng, Ding-Ming Kwai, Yung-Fa Chou
2013	—	`conf`	Enabling inter-die co-optimization in 3-D IC with TSVs. VLSI-DAT Chang-Tzu Lin, Tsu-Wei Tseng, Yung-Fa Chou, Chia-Hsin Lee, Ding-Ming Kwai
2013	—	`conf`	I-LUTSim: An iterative look-up table based thermal simulator for 3-D ICs. ASP-DAC Chi-Wen Pan, Yu-Min Lee, Pei-Yu Huang, Chi-Ping Yang, Chang-Tzu Lin, Chia-Hsin Lee, Yung-Fa Chou, Ding-Ming Kwai
2013	J	`jnl`	In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis. IEEE Trans. Very Large Scale Integr. Syst. Jhih-Wei You, Shi-Yu Huang, Yu-Hsiang Lin, Meng-Hsiu Tsai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
2013	J	`jnl`	Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers. IEEE Trans. Very Large Scale Integr. Syst. Hsiu-Ming Chang, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting Cheng, Cheng-Wen Wu
2013	J	`jnl`	Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai
2013	J	`jnl`	Reactivation of Spares for Off-Chip Memory Repair After Die Stacking in a 3-D IC With TSVs. IEEE Trans. Circuits Syst. I Regul. Pap. Yung-Fa Chou, Ding-Ming Kwai, Ming-Der Shieh, Cheng-Wen Wu
2013	Misc	`conf`	Special session 4C: Hot topic 3D-IC design and test. VTS Jin-Fu Li, Cheng-Wen Wu, Masahiro Aoyagi, Meng-Fan Marvin Chang, Ding-Ming Kwai
2013	—	`conf`	Worst-case IR-drop monitoring with 1GHz sampling rate. VLSI-DAT Chen-Hsiang Hsu, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou
2012	—	`conf`	3-D centric technology and realization with TSV. VLSI-DAT Chang-Tzu Lin, Chia-Hsin Lee, Tsu-Wei Tseng, Ding-Ming Kwai, Yung-Fa Chou
2012	—	`conf`	3D-IC BISR for stacked memories using cross-die spares. VLSI-DAT Chun-Chuan Chi, Yung-Fa Chou, Ding-Ming Kwai, Yu-Ying Hsiao, Cheng-Wen Wu, Yu-Tsao Hsing, Li-Ming Denq, Tsung-Hsiang Lin
2012	Misc	`conf`	A SAR ADC missing-decision level detection and removal technique. VTS Jiun-Lang Huang, X.-L. Huang, Yung-Fa Chou, Ding-Ming Kwai
2012	A	`conf`	A built-in self-test scheme for 3D RAMs. ITC Yun-Chao You, Che-Wei Chou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
2012	J	`jnl`	An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration. J. Electron. Test. Xuan-Lun Huang, Jiun-Lang Huang, Hung-I Chen, Chang-Yu Chen, Tseng Kuo-Tsai, Ming-Feng Huang, Yung-Fa Chou, Ding-Ming Kwai
2012	—	`conf`	Capturing the phantom of the power grid - on the runtime adaptive techniques for noise reduction. ASP-DAC Tao Wang, Pei-Wen Luo, Yu-Shih Su, Liang-Chia Cheng, Ding-Ming Kwai, Yiyu Shi
2012	A*	`conf`	Small delay testing for TSVs in 3-D ICs. DAC Shi-Yu Huang, Yu-Hsiang Lin, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter, Yung-Fa Chou, Ding-Ming Kwai
2011	—	`conf`	3D Stacked IC layout considering bond pad density and doubling for manufacturing yield improvement. ISQED Ding-Ming Kwai, Chang-Tzu Lin
2011	B	`conf`	A Pre- and Post-bond Self-Testing and Calibration Methodology for SAR ADC Array in 3-D CMOS Imager. ETS Xuan-Lun Huang, Ping-Ying Kang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai
2011	Misc	`conf`	A built-in self-test scheme for the post-bond test of TSVs in 3D ICs. VTS Yu-Jen Huang, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
2011	—	`conf`	A self-testing and calibration method for embedded successive approximation register ADC. ASP-DAC Xuan-Lun Huang, Ping-Ying Kang, Hsiu-Ming Chang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai, Cheng-Wen Wu
2011	—	`conf`	Developing through-silicon stacking process using 3-D CMOS imager as a test vehicle. ISOCC Ding-Ming Kwai, Ka-Yi Yeh
2011	A	`conf`	Thermal-aware on-line task allocation for 3D multi-core processor throughput optimization. DATE Chiao-Ling Lung, Yi-Lun Ho, Ding-Ming Kwai, Shih-Chieh Chang
2011	J	`jnl`	Yield Enhancement by Bad-Die Recycling and Stacking With Though-Silicon Vias. IEEE Trans. Very Large Scale Integr. Syst. Yung-Fa Chou, Ding-Ming Kwai, Cheng-Wen Wu
2010	—	`conf`	A Test Integration Methodology for 3D Integrated Circuits. Asian Test Symposium Che-Wei Chou, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
2010	A*	`conf`	An error tolerance scheme for 3D CMOS imagers. DAC Hsiu-Ming Chang, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting (Tim) Cheng, Cheng-Wen Wu
2010	—	`conf`	CAD reference flow for 3D via-last integrated circuits. ASP-DAC Chang-Tzu Lin, Ding-Ming Kwai, Yung-Fa Chou, Ting-Sheng Chen, Wen Ching Wu
2010	—	`conf`	Homogeneous integration for 3D IC with TSV. ASP-DAC Ding-Ming Kwai
2010	Misc	`conf`	On-chip testing of blind and open-sleeve TSVs for 3D IC before bonding. VTS Po-Yuan Chen, Cheng-Wen Wu, Ding-Ming Kwai
2010	—	`conf`	Performance Characterization of TSV in 3D IC via Sensitivity Analysis. Asian Test Symposium Jhih-Wei You, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
2009	—	`conf`	On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification. Asian Test Symposium Po-Yuan Chen, Cheng-Wen Wu, Ding-Ming Kwai
2006	—	`conf`	FlexiVia ROM Compiler Programmable on Different Via Layers Based on Top Metal Assignment. MTDT Ding-Ming Kwai, Yung-Fa Chou, Meng-Fan Chang, Su-Meng Yang, Ding-Sheng Chen, Min-Chung Hsu, Yu-Zhen Liao, Shiao-Yi Lin, Yu-Ling Sung, Chia-Hsin Lee, Hsin-Kun Hsu
2006	—	`conf`	SRAM Cell Current in Low Leakage Design. MTDT Ding-Ming Kwai, Ching-Hua Hsiao, Chung-Ping Kuo, Chi-Hsien Chuang, Min-Chung Hsu, Yi-Chun Chen, Yu-Ling Sung, Hsien-Yu Pan, Chia-Hsin Lee, Meng-Fan Chang, Yung-Fa Chou
2005	—	`conf`	Measurement and characterization of 6T SRAM cell current. MTDT Ching-Hua Hsiao, Ding-Ming Kwai
2005	—	`conf`	Via-programmable read-only memory design for full code coverage using a dynamic bit-line shielding technique. MTDT Meng-Fan Chang, Kuei-Ann Wen, Ding-Ming Kwai
2004	J	`jnl`	Comparing four classes of torus-based parallel architectures: Networkparameters and communication performance. Math. Comput. Model. Behrooz Parhami, Ding-Ming Kwai
2004	J	`jnl`	Incomplete J. Parallel Distributed Comput. Behrooz Parhami, Ding-Ming Kwai
2004	—	`conf`	Supply and Substrate Noise Tolerance Using Dynamic Tracking Clusters in Configurable Memory Designs. ISQED Meng-Fan Chang, Kuei-Ann Wen, Ding-Ming Kwai
2003	J	`jnl`	Parallel Architectures and Adaptation Algorithms for Programmable FIR Digital Filters With Fully Pipelined Data and Control Flows. J. Inf. Sci. Eng. Behrooz Parhami, Ding-Ming Kwai
2003	J	`jnl`	Practical considerations in applying Σ-Δ modulation-based analog BIST to sampled-data systems. IEEE Trans. Circuits Syst. II Express Briefs Hao-Chiao Hong, Jiun-Lang Huang, Kwang-Ting Cheng, Cheng-Wen Wu, Ding-Ming Kwai
2001	J	`jnl`	A Unified Formulation of Honeycomb and Diamond Networks. IEEE Trans. Parallel Distributed Syst. Behrooz Parhami, Ding-Ming Kwai
2001	J	`jnl`	Scalable Linear Array Architecture with Data-Driven Control for Ultrahigh-Speed Vector Quantization. J. VLSI Signal Process. Ding-Ming Kwai, Behrooz Parhami
2000	Misc	`conf`	Characterization and Generalization of Honeycomb and Diamond Networks. PDPTA Ding-Ming Kwai, Behrooz Parhami
2000	—	`conf`	etection of SRAM cell stability by lowering array supply voltage. Asian Test Symposium Ding-Ming Kwai, Hung-Wen Chang, Hung-Jen Liao, Ching-Hua Chiao, Yung-Fa Chou
1999	J	`jnl`	Correction to 'Periodically Regular Chordal Rings'. IEEE Trans. Parallel Distributed Syst. Behrooz Parhami, Ding-Ming Kwai
1999	J	`jnl`	Data-Driven Control Scheme for Linear Arrays: Application to a Stable Insertion Sorter. IEEE Trans. Parallel Distributed Syst. Behrooz Parhami, Ding-Ming Kwai
1999	J	`jnl`	Periodically Regular Chordal Rings. IEEE Trans. Parallel Distributed Syst. Behrooz Parhami, Ding-Ming Kwai
1999	J	`jnl`	Scalability of Programmable FIR Digital Filters. J. VLSI Signal Process. Ding-Ming Kwai, Behrooz Parhami
1998	J	`jnl`	Pruned Three-Dimensional Toroidal Networks. Inf. Process. Lett. Ding-Ming Kwai, Behrooz Parhami
1998	J	`jnl`	Tight Bounds on the Diameter of Gaussian Cubes. Comput. J. Ding-Ming Kwai, Behrooz Parhami
1997	B	`conf`	A Class of Fixed-Degree Cayley-Graph Interconnection Networks Derived by Pruning k-ary n-cubes. ICPP Ding-Ming Kwai, Behrooz Parhami
1997	J	`jnl`	An on-line fault diagnosis scheme for linear processor arrays. Microprocess. Microsystems Ding-Ming Kwai, Behrooz Parhami
1996	J	`jnl`	A Generalization of Hypercubic Networks Based on their Chordal Ring Structures. Parallel Process. Lett. Ding-Ming Kwai, Behrooz Parhami
1996	B	`conf`	Comparing the Performance Parameters of Two Network Structures for Scalable Massively Parallel Processors. MASCOTS Ding-Ming Kwai, Behrooz Parhami
1996	J	`jnl`	FFT computation with linear processor arrays using a data-driven control scheme. J. VLSI Signal Process. Ding-Ming Kwai, Behrooz Parhami
1996	—	`conf`	Periodically regular chordal rings: generality, scalability, and VLSI layout. SPDP Ding-Ming Kwai, Behrooz Parhami
1992	J	`jnl`	Data Flow Representation of Iterative Algorithms for Systolic Arrays. IEEE Trans. Computers Chein-Wei Jen, Ding-Ming Kwai
1989	J	`jnl`	Multi-dimensional parallel computing structures for regular iterative algorithms. Integr. Chein-Wei Jen, Ding-Ming Kwai