Dinesh Somasekhar

38 papers A* 3A 1C 3Misc 1Journal 19Unranked 11
YearRankTypeTitle / Venue / Authors
2016 J jnl
Guest Editorial Emerging Memories - Technology, Architecture and Applications (First Issue).
IEEE J. Emerg. Sel. Topics Circuits Syst.
Swaroop Ghosh, Rajiv V. Joshi, Dinesh Somasekhar, Xin Li
2016 J jnl
Guest Editorial Emerging Memories - Technology, Architecture and Applications (Second Issue).
IEEE J. Emerg. Sel. Topics Circuits Syst.
Swaroop Ghosh, Rajiv V. Joshi, Dinesh Somasekhar, Xin Li
2016 J jnl
Overview of Circuits, Systems, and Applications of Spintronics.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Swaroop Ghosh, Anirudh Iyengar, Seyedhamidreza Motaman, Rekha Govindaraj, Jae-Won Jang, Jinil Chung, Jongsun Park, Xin Li, Rajiv V. Joshi, Dinesh Somasekhar
2016 J jnl
System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators.
IEEE Trans. Very Large Scale Integr. Syst.
Ayan Paul, Sang Phill Park, Dinesh Somasekhar, Young Moon Kim, Nitin Borkar, Ulya R. Karpuzcu, Chris H. Kim
2014 J jnl
A 32 nm Embedded, Fully-Digital, Phase-Locked Low Dropout Regulator for Fine Grained Power Management in Digital Circuits.
IEEE J. Solid State Circuits
Samantak Gangopadhyay, Dinesh Somasekhar, James W. Tschanz, Arijit Raychowdhury
2014 — conf
Advanced memory topics.
CICC
Toshiaki Kirihata, Dinesh Somasekhar
2012 — conf
A fully-digital phase-locked low dropout regulator in 32nm CMOS.
VLSIC
Arijit Raychowdhury, Dinesh Somasekhar, James W. Tschanz, Vivek De
2012 J jnl
Direct Compare of Information Coded With Error-Correcting Codes.
IEEE Trans. Very Large Scale Integr. Syst.
Wei Wu, Dinesh Somasekhar, Shih-Lien Lu
2011 — conf
3DICs for tera-scale computing: a case study.
ISPD
Tanay Karnik, Dinesh Somasekhar, Shekhar Borkar
2011 J jnl
Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integration.
IET Comput. Digit. Tech.
Tanay Karnik, Dinesh Somasekhar, Shekhar Borkar
2010 J jnl
Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process.
IEEE J. Solid State Circuits
Dinesh Somasekhar, Balaji Srinivasan, Gunjan Pandya, Fatih Hamzaoglu, Muhammad M. Khellah, Tanay Karnik, Kevin Zhang
2010 A* conf
Reducing cache power with low-cost, multi-bit error-correcting codes.
ISCA
Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chishti, Wei Wu, Dinesh Somasekhar, Shih-Lien Lu
2010 — conf
Resilient design in scaled CMOS for energy efficiency.
ASP-DAC
James W. Tschanz, Keith A. Bowman, Muhammad M. Khellah, Chris Wilkerson, Bibiche M. Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep P. Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, Vivek De
2009 J jnl
2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology.
IEEE J. Solid State Circuits
Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Borkar, Vivek K. De, Ali Keshavarzi
2009 J jnl
Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits.
IEEE J. Solid State Circuits
Muhammad M. Khellah, Nam-Sung Kim, Yibin Ye, Dinesh Somasekhar, Tanay Karnik, Nitin Borkar, Gunjan Pandya, Fatih Hamzaoglu, Tom Coan, Yih Wang, Kevin Zhang, Clair Webb, Vivek De
2008 — conf
2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process.
ISSCC
Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Y. Borkar, Vivek De, Ali Keshavarzi
2007 J jnl
A 256-Kb Dual-V
IEEE J. Solid State Circuits
Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Nam-Sung Kim, Jason Howard, Gregory Ruhl, Murad Sunna, James W. Tschanz, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, Vivek De
2007 — conf
Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging.
ISSCC
James W. Tschanz, Nam-Sung Kim, Saurabh Dighe, Jason Howard, Gregory Ruhl, Sriram R. Vangal, Siva G. Narendra, Yatin Hoskote, Howard Wilson, Carol Lam, Matthew Shuman, Carlos Tokunaga, Dinesh Somasekhar, Stephen Tang, David Finan, Tanay Karnik, Nitin Borkar, Nasser A. Kurd, Vivek De
2007 — conf
Fine-Grained Redundancy in Adders.
ISQED
Patrick Ndai, Shih-Lien Lu, Dinesh Somasekhar, Kaushik Roy
2006 — conf
A 4.2GHz 0.3mm2 256kb Dual-V
ISSCC
Muhammad M. Khellah, Nam-Sung Kim, Jason Howard, Gregory Ruhl, Yibin Ye, James W. Tschanz, Dinesh Somasekhar, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, Vivek De
2006 C conf
Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches.
ISCAS
Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Vivek De
2005 — conf
A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications.
ESSCIRC
Dinesh Somasekhar, Shih-Lien Lu, Bradley A. Bloechel, Greg Dermer, Konrad Lai, Sjeljar Borkar, Vivek De
2003 J jnl
A 6-GHz 16-kB L1 cache in a 100-nm dual-V
IEEE J. Solid State Circuits
Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Ali Farhang, Vivek De
2003 — conf
Bitline leakage equalization for sub-100nm caches.
ESSCIRC
Atila Alvandpour, Dinesh Somasekhar, Ram Krishnamurthy, Vivek De, Shekhar Borkar, Christer Svensson
2002 J jnl
5-GHz 32-bit integer execution core in 130-nm dual-V
IEEE J. Solid State Circuits
Sriram R. Vangal, Mark A. Anders, Nitin Borkar, Erik Seligman, Venkatesh Govindarajulu, Vasantha Erraguntla, Howard Wilson, Amaresh Pangal, Venkat Veeramachaneni, James W. Tschanz, Yibin Ye, Dinesh Somasekhar, Bradley A. Bloechel, Gregory E. Dermer, Ram K. Krishnamurthy, Krishnamurthy Soumyanath, Sanu Mathew, Siva G. Narendra, Mircea R. Stan, Scott Thompson, Vivek De, Shekhar Borkar
2002 J jnl
Leakage control with efficient use of transistor stacks in single threshold CMOS.
IEEE Trans. Very Large Scale Integr. Syst.
Mark C. Johnson, Dinesh Somasekhar, Lih-Yih Chiou, Kaushik Roy
2002 J jnl
Skewed CMOS: noise-tolerant high-performance low-power static circuit family.
IEEE Trans. Very Large Scale Integr. Syst.
Alexandre Solomatnikov, Dinesh Somasekhar, Naran Sirisantana, Kaushik Roy
2000 A* conf
Dynamic noise analysis in precharge-evaluate circuits.
DAC
Dinesh Somasekhar, Seung Hoon Choi, Kaushik Roy, Yibin Ye, Vivek De
2000 C conf
Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family.
ICCD
Alexandre Solomatnikov, Kaushik Roy, Cheng-Kok Koh, Dinesh Somasekhar
1999 A* conf
Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS.
DAC
Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy
1999 J jnl
Models and algorithms for bounds on leakage in CMOS circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy
1999 C conf
Switching Characteristics of Generalized Array Multiplier Architectures and their Applications to Low Power Design.
ICCD
Khurram Muhammad, Dinesh Somasekhar, Kaushik Roy
1998 — conf
IDD Waveforms Analysis for Testing of Domino and Low Voltage Static CMOS Circuits.
Great Lakes Symposium on VLSI
Hendrawan Soeleman, Dinesh Somasekhar, Kaushik Roy
1998 J jnl
LVDCSL: a high fan-in, high-performance, low-voltage differential current switch logic family.
IEEE Trans. Very Large Scale Integr. Syst.
Dinesh Somasekhar, Kaushik Roy
1997 A conf
LVDCSL: low voltage differential current switch logic, a robust low power DCSL family.
ISLPED
Dinesh Somasekhar, Kaushik Roy
1996 J jnl
Differential current switch logic: a low power DCVS logic family.
IEEE J. Solid State Circuits
Dinesh Somasekhar, Kaushik Roy
1993 J jnl
A 230-MHz half-bit level pipelined multiplier using true single-phase clocking.
IEEE Trans. Very Large Scale Integr. Syst.
Dinesh Somasekhar, V. Visvanathan
1993 Misc conf
A 230MHz Half Bit Level Pipelined Multiplier Using True Single Phase Clocking.
VLSI Design
Dinesh Somasekhar, V. Visvanathan