Dinesh Pamunuwa

46 papers A 7C 8Misc 2Journal 9Unranked 19

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	NL2GDS: LLM-aided interface for Open Source Chip Design. CoRR Max Eland, Jeyan Thiyagalingam, Dinesh Pamunuwa, Roshan Weerasekera
2025	—	`conf`	A Fault-Tolerant Voter Circuit in NEM Technology. DFT Dominik Rudolf, Ardavan Elahi, Axel Jantsch, Dinesh Pamunuwa
2025	—	`conf`	DT2HDL: A Binary Decision Tree to HDL Generation Tool. ISQED Qijia Tang, Dinesh Pamunuwa, Roshan Weerasekera
2025	C	`conf`	Measurement and Analysis of Dynamic Energy Consumption in Microelectromechanical Relays. ISCAS Qi Tang, Elliott Worsey, Mukesh Kumar Kulsreshath, Yue Fan, Yingying Li, Simon J. Bleiker, Harold M. H. Chong, Frank Niklaus, Dinesh Pamunuwa
2025	—	`conf`	Muller C-Element for NEMS. ASYNC Philipp Lehninger, Axel Jantsch, Andreas Steininger, Elliott Worsey, Victor Marot, Dinesh Pamunuwa
2025	A	`conf`	Nanoelectromechanical Binary Comparator for Edge-Computing Applications. DATE Victor Marot, Manu Bala Krishnan, Mukesh Kumar Kulsreshath, Elliott Worsey, Roshan Weerasekera, Dinesh Pamunuwa
2025	C	`conf`	Nanomechanical Relay-based Switchblock For FPGA Interconnect. ISCAS Victor Marot, Dinesh Pamunuwa
2024	C	`conf`	Nanoelectromechanical analog-to-digital converter for low power and harsh environments. ISCAS Elliott Worsey, Qi Tang, Manu Bala Krishnan, Mukesh Kumar Kulsreshath, Dinesh Pamunuwa
2018	J	`jnl`	Performance Analysis of Nanoelectromechanical Relay-Based Field-Programmable Gate Arrays. IEEE Access Tian Qin, Simon J. Bleiker, Sunil Rana, Frank Niklaus, Dinesh Pamunuwa
2015	A	`conf`	Design Methodologies, Models and Tools for Very-Large-Scale Integration of NEM Relay-Based Circuits. ICCAD Tian Qin, Sunil Rana, Dinesh Pamunuwa
2015	J	`jnl`	Zero-load predictive model for performance analysis in deflection routing NoCs. Microprocess. Microsystems Awet Yemane Weldezion, Matt Grange, Axel Jantsch, Hannu Tenhunen, Dinesh Pamunuwa
2014	J	`jnl`	Energy and Latency Optimization in NEM Relay-Based Digital Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. Sunil Rana, Tian Qin, Antonios Bazigos, Daniel Grogg, Michel Despont, Christopher Lawrence Ayala, Christoph Hagleitner, Adrian Mihai Ionescu, Roberto Canegallo, Dinesh Pamunuwa
2013	—	`conf`	A scalable multi-dimensional NoC simulation model for diverse spatio-temporal traffic patterns. 3DIC Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuwa, Axel Jantsch, Hannu Tenhunen
2013	C	`conf`	Modelling NEM relays for digital circuit applications. ISCAS Sunil Rana, Tian Qin, Dinesh Pamunuwa, Daniel Grogg, Michel Despont, Yu Pu, Christoph Hagleitner
2011	C	`conf`	3-D integration and the limits of silicon computation. VLSI-SoC Dinesh Pamunuwa, Matthew Grange, Roshan Weerasekera, Axel Jantsch
2011	A	`conf`	Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning. ICCAD Matthew Grange, Axel Jantsch, Roshan Weerasekera, Dinesh Pamunuwa
2011	—	`conf`	Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks. NOCS Matt Grange, Roshan Weerasekera, Dinesh Pamunuwa, Axel Jantsch, Awet Yemane Weldezion
2011	—	`ch.`	The Promises and Limitations of 3-D Integration. 3D Integration for NoC-based SoC Architectures Axel Jantsch, Matthew Grange, Dinesh Pamunuwa
2010	A	`conf`	On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits. DATE Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, Hannu Tenhunen
2009	—	`conf`	Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits. 3DIC Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, Hannu Tenhunen, Li-Rong Zheng
2009	C	`conf`	Design of Robust Molecular Electronic Circuits. ISCAS Ci Lei, Dinesh Pamunuwa, Steven Bailey, Colin Lambert
2009	—	`conf`	Designing Reliable Digital Molecular Electronic Circuits. NanoNet Ci Lei, Dinesh Pamunuwa, Steven Bailey, Colin Lambert
2009	—	`conf`	Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh. 3DIC Matt Grange, Awet Yemane Weldezion, Dinesh Pamunuwa, Roshan Weerasekera, Zhonghai Lu, Axel Jantsch, Dave Shippen
2009	—	`conf`	Scalability of network-on-chip communication architecture for 3-D meshes. NOCS Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuwa, Zhonghai Lu, Axel Jantsch, Roshan Weerasekera, Hannu Tenhunen
2009	J	`jnl`	Two-Dimensional and Three-Dimensional Integration of Heterogeneous Electronic Systems Under Cost, Performance, and Technological Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
2008	—	`conf`	Application of Molecular Electronics Devices in Digital Circuit Design. NanoNet Ci Lei, Dinesh Pamunuwa, Steven Bailey, Colin Lambert
2008	A	`conf`	Memory Technology for Extended Large-Scale Integration in Future Electronics Applications. DATE Dinesh Pamunuwa
2008	J	`jnl`	Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime. IEEE Trans. Very Large Scale Integr. Syst. Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
2007	Misc	`conf`	Delay-Balanced Smart Repeaters for On-Chip Global Signaling. VLSI Design Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
2007	—	`conf`	Early selection of system implementation choice among SoC, SoP and 3-D Integration. SoCC Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen
2007	A	`conf`	Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs. ICCAD Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen
2006	—	`conf`	Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime. SLIP Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
2005	J	`jnl`	Modeling delay and noise in arbitrarily coupled RC trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dinesh Pamunuwa, Shauki Elassaad, Hannu Tenhunen
2005	—	`conf`	Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses. PATMOS Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen
2004	J	`jnl`	A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime. Integr. Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch, Hannu Tenhunen
2004	—	`conf`	Crosstalk immune interconnect driver design. SoC Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen
2003	—	`conf`	A global wire planning scheme for Network-on-Chip. ISCAS (4) Jian Liu, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen
2003	A	`conf`	Analytic Modeling of Interconnects for Deep Sub-Micron Circuits. ICCAD Dinesh Pamunuwa, Shauki Elassaad, Hannu Tenhunen
2003	—	`conf`	Closed form metrics to accurately model the response in general arbitrarily-coupled RC trees. ISCAS (4) Dinesh Pamunuwa, Shauki Elassaad
2003	C	`conf`	Layout, Performance and Power Trade-Offs in Mesh-Based Network-on-Chip Architectures. VLSI-SOC Dinesh Pamunuwa, Johnny Öberg, Li-Rong Zheng, Mikael Millberg, Axel Jantsch
2003	J	`jnl`	Maximizing throughput over parallel wire structures in the deep submicrometer regime. IEEE Trans. Very Large Scale Integr. Syst. Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
2002	—	`conf`	On Dynamic Delay and Repeater Insertion in Distributed Capacitively Coupled Interconnects. ISQED Dinesh Pamunuwa, Hannu Tenhunen
2002	—	`conf`	On dynamic delay and repeater insertion. ISCAS (1) Hannu Tenhunen, Dinesh Pamunuwa
2002	—	`conf`	Optimising bandwidth over deep sub-micron interconnect. ISCAS (4) Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen
2001	Misc	`conf`	Repeater Insertion To Minimise Delay In Coupled Interconnects. VLSI Design Dinesh Pamunuwa, Hannu Tenhunen
2000	C	`conf`	Combating digital noise in high speed ULSI circuits using binary BCH encoding. ISCAS Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen