Dinesh Kushwaha

19 papers C 3Misc 2Journal 2Unranked 12

Year	Rank	Type	Title / Venue / Authors
2026	Misc	`conf`	An Energy Efficient Pulse Accumulator Circuit (PAC) Based Multi-Bit Time Domain Compute in-Memory Architecture. VLSID Subhradip Chakraborty, Dinesh Kushwaha
2025	C	`conf`	A 1.91 POPS/W Energy-Efficient SRAM Based Signed Multi-Bit Time Domain CIM Architecture. ISCAS Subhradip Chakraborty, Dinesh Kushwaha, Himanshu Ranjan, Sudeb Dasgupta
2025	—	`conf`	A Robust 4T1C eDRAM Compute-in-Memory Architecture for Inference Applications. NewCAS Aditya Kumar Singh, Dinesh Kushwaha, Sudeb Dasgupta
2025	—	`conf`	A Robust Fully Differential MAC Scheme Using Dummy Rows to Enhance the Signal Margin of Analog Compute-in-Memory Architecture. NewCAS Dinesh Kushwaha, Sudeb Dasgupta, Anand Bulusu
2024	—	`conf`	An Area and Energy-Efficient SRAM Based Time - Domain Compute-In-Memory Architecture For BNN. AICAS Subhradip Chakraborty, Dinesh Kushwaha, Anand Bulusu, Sudeb Dasgupta
2024	—	`conf`	An Energy-Efficient High Signal Margin Analog Compute-In-Memory Architecture. LASCAS Dinesh Kushwaha, Rajat Kohli, Jwalant Mishra, Jainendra Singh, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2024	—	`conf`	An Energy-Efficient SRAM-Based Charge Domain Compute In-Memory Architecture. NewCAS Anmol Singla, Dinesh Kushwaha, Gulyawar Aman, Shubhradin Chakraborty, Abhishek Goel, Anand Bulusu, Sudeb Dasgupta
2024	—	`conf`	An Energy-Efficient Time Domain Based Compute In-Memory Architecture for Binary Neural Network. ISQED Subhradip Chakraborty, Dinesh Kushwaha, Abhishek Goel, Anmol Singla, Anand Bulusu, Sudeb Dasgupta
2024	J	`jnl`	Multi-Bit Compute-In Memory Architecture Using a C-2C Ladder Network. IEEE Trans. Circuits Syst. II Express Briefs Dinesh Kushwaha, Jaya Kumar Abotula, Rajat Kohli, Jwalant Mishra, Sudeb Dasgupta, Anand Bulusu
2024	—	`conf`	SRAM-Based Analog Compute-In-Memory Architecture Using C-2C Ladder And Signal Margin Assisted Design Methodology. ISQED Dinesh Kushwaha, Ashish Joshi, Abhishek Goel, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2024	C	`conf`	SRAM-Based Hybrid Analog Compute-In-memory Architecture to Enhance the Signal Margin. ISCAS Dinesh Kushwaha, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2024	—	`conf`	Time-Domain-Based Non-volatile In-Memory Computing Architecture Using FeFETs for Binary Neural Network. ISQED Aditya Sharma, Vatsal Dixit, Dinesh Kushwaha, Nitanshu Chauhan, Vishal Kumar Saxena, Sudeb Dasgupta, Anand Bulusu
2024	—	`conf`	Variation-Aware Design Methodology for SRAM-Based Multi-Bit Analog Compute-in-Memory Architecture. NewCAS Dinesh Kushwaha, Rajiv V. Joshi, Anand Bulusu, Sudeb Dasgupta
2023	—	`conf`	A Fully Differential 4-Bit Analog Compute-In-Memory Architecture for Inference Application. AICAS Dinesh Kushwaha, Rajat Kohli, Jwalant Mishra, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2023	Misc	`conf`	An Energy-Efficient Multi-bit Current-based Analog Compute-In-Memory Architecture and design Methodology. VLSID Dinesh Kushwaha, Ashish Joshi, Neha Gupta, Aditya Sharma, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2022	C	`conf`	A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing. ISCAS Dinesh Kushwaha, Aditya Sharma, Neha Gupta, Ritik Raj, Ashish Joshi, Jwalant Mishra, Rajat Kohli, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2022	—	`conf`	A Multibit MAC Scheme using Switched Capacitor based 3C Multiplier for Analog Compute In-Memory Architecture. ICECS 2022 Neha Gupta, Ashish Joshi, Dinesh Kushwaha, Vinod Menezes, Rashmi Sachan, Sudeb Dasgupta, Anand Bulusu
2022	J	`jnl`	An Energy-Efficient High CSNR XNOR and Accumulation Scheme for BNN. IEEE Trans. Circuits Syst. II Express Briefs Dinesh Kushwaha, Ashish Joshi, Chaudhry Indra Kumar, Neha Gupta, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2016	—	`conf`	A 415 nW, 0.8 V, voltage reference circuit using MOSFETs in saturation and sub-threshold regions. ICIIS Dinesh Kushwaha, D. K. Mishra