Dinesh Gaitonde

20 papers A 6B 3Misc 2Unranked 9

Year	Rank	Type	Title / Venue / Authors
2025	Misc	`conf`	Guaranteed Yet Hard to Find: Uncovering FPGA Routing Convergence Paradox. FCCM Shashwat Shrivastava, Stefan Nikolic, Sun Tanaka, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic
2024	—	`conf`	Sensing Timing Margin Contingencies in the Programmable Fabric of FPGAs. ICFPT Arun Iyer, Nishant Pawar, Dinesh Gaitonde, Nanditha Rao
2023	—	`conf`	AMD Next-Generation FPGA Built from Chiplets. HCS Dinesh Gaitonde
2023	A	`conf`	IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck. ICCAD Shashwat Shrivastava, Stefan Nikolic, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic
2023	A	`conf`	Mitigating the Last-Mile Bottleneck: A Two-Step Approach For Faster Commercial FPGA Routing. FPGA Shashwat Shrivastava, Stefan Nikolic, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic
2023	Misc	`conf`	Modular and Lean Architecture with Elasticity for Sparse Matrix Vector Multiplication on FPGAs. FCCM Abhishek Kumar Jain, Chirag Ravishankar, Hossein Omidian, Sharan Kumar, Maithilee Kulkarni, Aashish Tripathi, Dinesh Gaitonde
2022	—	`conf`	100% Visibility at MHz Speed: Efficient Soft Scan-Chain Insertion on AMD/Xilinx FPGAs. ARC Hossein Omidian, Eddie Hung, Dinesh Gaitonde
2021	—	`conf`	Sparse Deep Neural Network Acceleration on HBM-Enabled FPGA Platform. HPEC Abhishek Kumar Jain, Sharan Kumar, Aashish Tripathi, Dinesh Gaitonde
2020	B	`conf`	A Domain-Specific Architecture for Accelerating Sparse Matrix Vector Multiplication on FPGAs. FPL Abhishek Kumar Jain, Hossein Omidian, Henri Fraisse, Mansimran Benipal, Lisa Liu, Dinesh Gaitonde
2019	A	`conf`	Network-on-Chip Programmable Platform in Versal FPGA Ian Swarbrick, Dinesh Gaitonde, Sagheer Ahmad, Brian Gaide, Ygal Arbel
2019	—	`conf`	Versal Network-on-Chip (NoC). Hot Interconnects Ian Swarbrick, Dinesh Gaitonde, Sagheer Ahmad, Bala Jayadev, Jeff Cuppett, Abbas Morshed, Brian Gaide, Ygal Arbel
2019	A	`conf`	Xilinx Adaptive Compute Acceleration Platform: Versal FPGA Brian Gaide, Dinesh Gaitonde, Chirag Ravishankar, Trevor Bauer
2018	B	`conf`	A SAT-based Timing Driven Place and Route Flow for Critical Soft IP. FPL Henri Fraisse, Dinesh Gaitonde
2018	B	`conf`	Placement Strategies for 2.5D FPGA Fabric Architectures. FPL Chirag Ravishankar, Dinesh Gaitonde, Trevor Bauer
2018	—	`conf`	SAT Based Place-And-Route for High-Speed Designs on 2.5D FPGAs. FPT Chirag Ravishankar, Henri Fraisse, Dinesh Gaitonde
2016	A	`conf`	Boolean Satisfiability-Based Routing and Its Application to Xilinx UltraScale Clock Network. FPGA Henri Fraisse, Abhishek Joshi, Dinesh Gaitonde, Alireza Kaviani
2015	A	`conf`	Enhancements in UltraScale CLB Architecture. FPGA Shant Chandrakar, Dinesh Gaitonde, Trevor Bauer
2014	—	`conf`	High capacity and high performance 20nm FPGAs. Hot Chips Symposium Steve Young, Dinesh Gaitonde
1999	—	`conf`	Instruction level power model of microcontrollers. ISCAS (1) Chaitali Chakrabarti, Dinesh Gaitonde
1998	—	`conf`	An overview of library characterization in semi-custom design. CICC Binay Ackalloor, Dinesh Gaitonde