Dinesh Bhatia - RankMe

89 papers A* 1A 5B 13C 11Misc 13Journal 24Unranked 22

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	Advancing Towards a Wearable Ultrasound Sensor for Real-Time Bladder Volume Monitoring to Reduce Catheterization in Surgical Settings. EMBC Rouzbeh Molaei Imenabadi, Mojtaba Hasanpour Avanji, Dinesh Bhatia, Katherine Brown
2023	J	`jnl`	Application of Machine Learning in FPGA EDA Tool Development. IEEE Access Pingakshya Goswami, Dinesh Bhatia
2023	C	`conf`	Enhancing Student Engagement in Engineering and Education Through Virtual Reality: A Survey-Based Analysis. TENCON Dinesh Bhatia, Henrik Hesse
2023	J	`jnl`	Feed Forward Neural Network BCI-based trajectory-controlled Lower-limb exoskeleton: a Biomechatronics Approach. Int. J. Robotics Autom. Ganesh Roy, Dinesh Bhatia, Subhasis Bhaumik
2023	J	`jnl`	Machine learning based fast and accurate High Level Synthesis design space exploration: From graph to synthesis. Integr. Pingakshya Goswami, Benjamin Carrión Schäfer, Dinesh Bhatia
2022	—	`conf`	MLSBench: A Benchmark Set for Machine Learning based FPGA HLS Design Flows. LASCAS Pingakshya Goswami, Masoud Shahshahani, Dinesh Bhatia
2022	—	`conf`	PPA Based CNN Architecture Explorer. LASCAS Masoud Shahshahani, Dinesh Bhatia
2022	—	`conf`	Predicting Post-Route Quality of Results Estimates for HLS Designs using Machine Learning. ISQED Pingakshya Goswami, Dinesh Bhatia
2022	J	`jnl`	Predicting Post-Route Quality of Results Estimates for HLS Designs using Machine Learning. CoRR Pingakshya Goswami, Dinesh Bhatia
2022	Misc	`conf`	Robust Estimation of FPGA Resources and Performance from CNN Models. VLSID Pingakshya Goswami, Masoud Shahshahani, Dinesh Bhatia
2021	Misc	`conf`	An Automated Tool for Implementing Deep Neural Networks on FPGA. VLSID Masoud Shahshahani, Mohammad Sabri Abrebekoh, Bahareh Khabbazan, Dinesh Bhatia
2021	—	`conf`	Resource and Performance Estimation for CNN Models using Machine Learning. ISVLSI Masoud Shahshahani, Dinesh Bhatia
2020	J	`jnl`	Automated Floorplanning for Partially Reconfigurable Designs on Heterogenrous FPGAs. CoRR Pingakshya Goswami, Dinesh Bhatia
2020	J	`jnl`	Empirical greedy machine-based automatic liver segmentation in CT images. IET Image Process. Gajendra Kumar Mourya, Dinesh Bhatia, Akash Handique
2020	A	`conf`	MLSBench: A Synthesizable Dataset of HLS Designs to Support ML Based Design Flows. FPGA Pingakshya Goswami, Masoud Shahshahani, Dinesh Bhatia
2017	C	`conf`	Portable impedance measurement device for sweat based glucose detection. BSN Athul Asokan Thulasi, Dinesh Bhatia, Poras T. Balsara, Shalini Prasad
2016	J	`jnl`	Comparison of muscle activation patterns among healthy males and females during different lower limb movements. Int. J. Medical Eng. Informatics Shilpi Mathur, Manvinder Kaur, Dinesh Bhatia, Suresh Verma
2016	A	`conf`	Floorplanning of Partially Reconfigurable Design on Heterogeneous FPGA (Abstract Only). FPGA Pingakshya Goswami, Dinesh Bhatia
2014	J	`jnl`	A smart door access system using finger print biometric system. Int. J. Medical Eng. Informatics Anu, Dinesh Bhatia
2014	J	`jnl`	Design of smart functional electric stimulator for physically challenged person. Int. J. Medical Eng. Informatics Devender Singh, Manvinder Kaur, Dinesh Bhatia
2014	J	`jnl`	Quantitative measurement of carbon monoxide level in closed environment. Int. J. Medical Eng. Informatics Abhishek Agarwal, Dinesh Bhatia
2013	—	`conf`	Antenna designs for wearable body sensor communication. PETRA Dinesh Bhatia, A. L. Praveen Aroul
2013	J	`jnl`	Growth of neural engineering and neuro-mechanics in India: physically challenged looking towards a bright future. Int. J. Medical Eng. Informatics Dinesh Bhatia
2013	J	`jnl`	Impact of communication technology on human brain activity: mobile phone vs. landline phone. Int. J. Medical Eng. Informatics Aruna Tyagi, Manoj Duhan, Dinesh Bhatia
2011	—	`conf`	Study of performance and propagation characteristics of wire and planar structures around human body. EMBC A. L. Praveen Aroul, Dinesh Bhatia
2008	B	`conf`	A dynamic temperature control simulation system for FPGAs. FPL Shilpa Bhoj, Dinesh Bhatia
2008	C	`conf`	Early stage FPGA interconnect leakage power estimation. ICCD Shilpa Bhoj, Dinesh Bhatia
2008	—	`conf`	Power efficient multi-band contextual activity monitoring for assistive environments. PETRA A. L. Praveen Aroul, Achutan Manohar, Dinesh Bhatia, Leonardo Estevez
2007	B	`conf`	Pre-route Interconnect Capacitance and Power Estimation in FPGAs. FPL Shilpa Bhoj, Dinesh Bhatia
2007	C	`conf`	Thermal Modeling and Temperature Driven Placement for FPGAs. ISCAS Shilpa Bhoj, Dinesh Bhatia
2006	—	`conf`	A leakage aware design methodology for power-gated programmable architectures. FPT Narayan Subramanian, Rajarshee P. Bharadwaj, Dinesh Bhatia
2006	Misc	`conf`	Exploring Logic Block Granularity in Leakage Tolerant FPGA. VLSI Design Rajan Konar, Rajarshee P. Bharadwaj, Dinesh Bhatia, Poras T. Balsara
2006	—	`conf`	Generic Network Interfaces for Plug and Play NoC Based Architecture. ARC Sanjay Pratap Singh, Shilpa Bhoj, Dheera Balasubramanian, Tanvi Nagda, Dinesh Bhatia, Poras T. Balsara
2006	J	`jnl`	Interconnect estimation for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. PariVallal Kannan, Dinesh Bhatia
2005	J	`jnl`	A priori wirelength and interconnect estimation based on circuit characteristic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shankar Balachandran, Dinesh Bhatia
2005	A	`conf`	Design and Implementation of Configurable W-CDMA Rake Receiver Architectures on FPGA. IPDPS Mukesh Chugh, Dinesh Bhatia, Poras T. Balsara
2005	—	`conf`	Exploiting temporal idleness to reduce leakage power in programmable architectures. ASP-DAC Rajarshee P. Bharadwaj, Rajan Konar, Poras T. Balsara, Dinesh Bhatia
2005	—	`conf`	FPGA Architecture for Standby Power Management. FPT Rajarshee P. Bharadwaj, Rajan Konar, Dinesh Bhatia, Poras T. Balsara
2005	J	`jnl`	FPGA based EBCOT architecture for JPEG 2000. Microprocess. Microsystems Manjunath Gangadhar, Dinesh Bhatia
2005	Misc	`conf`	Placement and Routing for 3D-FPGAs Using Reinforcement Learning and Support Vector Machines. VLSI Design R. Manimegalai, E. Siva Soumya, Vaishnavi Muralidharan, Balaraman Ravindran, V. Kamakoti, Dinesh Bhatia
2005	B	`conf`	Timing Aware Interconnect Prediction Models for FPGAs. FPL Shankar Balachandran, Dinesh Bhatia
2004	Misc	`conf`	Estimating Pre-Placement FPGA Interconnection Requirements. VLSI Design PariVallal Kannan, Dinesh Bhatia
2004	J	`jnl`	On metrics for comparing interconnect estimation methods for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia
2003	—	`conf`	A-priori wirelength and interconnect estimation based on circuit characteristics. SLIP Shankar Balachandran, Dinesh Bhatia
2003	—	`conf`	FPGA based EBCOT architecture for JPEG 2000. FPT Manjunath Gangadhar, Dinesh Bhatia
2003	C	`conf`	Interconnect Estimation for FPGAs under Timing Driven Domains. ICCD PariVallal Kannan, Dinesh Bhatia
2003	J	`jnl`	On Using Tabu Search for Design Automation of VLSI Systems. J. Heuristics John Marty Emmert, Sandeep Lodha, Dinesh Bhatia
2002	—	`conf`	On Routing Demand and Congestion Estimation for FPGAs. ASP-DAC/VLSI Design Shankar Balachandran, PariVallal Kannan, Dinesh Bhatia
2002	A*	`conf`	On metrics for comparing routability estimation methods for FPGAs. DAC PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia
2002	B	`conf`	Rapid and Reliable Routability Estimation for FPGAs. FPL PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia
2001	B	`conf`	Tightly Integrated Placement and Routing for FPGAs. FPL PariVallal Kannan, Dinesh Bhatia
2001	B	`conf`	fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits. FPL PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia
2000	J	`jnl`	Bounds, designs and layouts for multi-terminal FPIC architectures. Integr. Dinesh Bhatia, James Haralambides
2000	J	`jnl`	Resource requirements and layouts for field programmable interconnection chips. IEEE Trans. Very Large Scale Integr. Syst. Dinesh Bhatia, James Haralambides
1999	A	`conf`	A Methodology for Fast FPGA Floorplanning. FPGA John Marty Emmert, Dinesh Bhatia
1999	—	`conf`	Clustering to improve bi-partition quality and run time. ISCAS (6) Gregory Tumbush, Dinesh Bhatia
1999	—	`conf`	Fast timing driven placement using tabu search. ISCAS (1) John Marty Emmert, Dinesh Bhatia
1999	B	`conf`	NEBULA: A Partially and Dynamically Reconfigurable Architecture. FPL Dinesh Bhatia, Kuldeep S. Simha, PariVallal Kannan
1999	B	`conf`	Tabu Search: Ultra-Fast Placement for FPGAs. FPL John Marty Emmert, Dinesh Bhatia
1999	J	`jnl`	Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers. IEEE Trans. Computers Karthikeya M. Gajjala Purna, Dinesh Bhatia
1998	C	`conf`	Clock-skew constrained placement for row based designs. ICCD Natesan Venkateswaran, Dinesh Bhatia
1998	C	`conf`	Emulating Large Designs on Small Reconfigurable Hardware. International Workshop on Rapid System Prototyping Karthikeya M. Gajjala Purna, Dinesh Bhatia
1998	B	`conf`	Fast Floorplanning for FPGAs. FPL John Marty Emmert, Akash Randhar, Dinesh Bhatia
1998	C	`conf`	Partitioning in time: a paradigm for reconfigurable computing. ICCD Karthikeya M. Gajjala Purna, Dinesh Bhatia
1998	B	`conf`	REACT: Reactive Environment for Runtime Reconfiguration. FPL Dinesh Bhatia, PariVallal Kannan, Kuldeep S. Simha, Karthikeya M. Gajjala Purna
1998	Misc	`conf`	Temporal Partitioning and Scheduling for Reconfigurable Computing. FCCM Karthikeya M. Gajjala Purna, Dinesh Bhatia
1998	Misc	`conf`	Timing Driven Multi-FPGA Board Partitioning. VLSI Design Raghu Burra, Dinesh Bhatia
1997	—	`conf`	A constructive method for data path area estimation during high-level VLSI synthesis. ASP-DAC Natesan Venkateswaran, Anurag Gupta, Srinivas Katkoori, Dinesh Bhatia, Ranga Vemuri
1997	Misc	`conf`	Macro Block Based FPGA Floorplanning. VLSI Design Jianzhong Shi, Akash Randhar, Dinesh Bhatia
1997	B	`conf`	Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement. FPL John Marty Emmert, Dinesh Bhatia
1997	C	`conf`	Partitioning Under Timing and Area Constraints. ICCD Gregory Tumbush, Dinesh Bhatia
1997	A	`conf`	Performance Driven Floorplanning for FPGA Based Designs. FPGA Jianzhong Shi, Dinesh Bhatia
1997	Misc	`conf`	Reconfigurable Computing. VLSI Design Dinesh Bhatia
1996	J	`jnl`	A Multi-Terminal Net Router for Field-Programmable Gate Arrays. VLSI Design Dinesh Bhatia, Amit Chowdhary
1996	Misc	`conf`	Clock-Skew Constrained Cell Placement. VLSI Design Natesan Venkateswaran, Dinesh Bhatia
1996	J	`jnl`	Field-Programmable Gate Arrays. VLSI Design Dinesh Bhatia
1996	J	`jnl`	Greedy Segmented Channel Router. VLSI Design Dinesh Bhatia, V. Shankar
1996	C	`conf`	Multiway Partitioner for High Performance FPGA Based Board Architecture. ICCD Vijayanand Sankarasubramanian, Dinesh Bhatia
1996	B	`conf`	RACE: Reconfigurable and Adaptive Computing Environment. FPL Doug Smith, Dinesh Bhatia
1995	J	`jnl`	Pseudo-exhaustive built-in TPG for sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dimitrios Kagaris, Spyros Tragoudas, Dinesh Bhatia
1995	Misc	`conf`	Resource requirements for field programmable interconnection chips. VLSI Design Dinesh Bhatia, James Haralambides
1994	Misc	`conf`	Detailed Routing of Multi-Terminal Nets in FPGAs. VLSI Design Amit Chowdhary, Dinesh Bhatia
1994	—	`conf`	Generalized segmented channel routing. Great Lakes Symposium on VLSI V. Shankar, Dinesh Bhatia
1994	Misc	`conf`	Hierarchical Reconfiguration of VLSI/WSI Arrays. VLSI Design Dinesh Bhatia, Ramesh Rajagopalan, Srinivas Katkoori
1994	—	`conf`	Mathematical model for routability analysis of FPGAs. Great Lakes Symposium on VLSI Dinesh Bhatia, Amit Chowdhary, Spyros Tragoudas
1993	C	`conf`	Pseudoexhaustive BIST for Sequential Circuits. ICCD Dimitrios Kagaris, Spyros Tragoudas, Dinesh Bhatia
1992	B	`conf`	Improved Algorithms for Routing on Two-Dimensional Grids. WG Dinesh Bhatia, Frank Thomson Leighton, Fillia Makedon, Carolyn Haibt Norton
1990	—	`conf`	Efficient Reconfiguration of WSI Arrays. ICSI Dinesh Bhatia, Frank Thomson Leighton, Fillia Makedon
1990	—	`conf`	Restructuring wafers for maximum yield and some applications of WSI. SPDP Dinesh Bhatia