Dimitris Nikolos

125 papers A 9B 1C 11Misc 9Journal 44Unranked 51

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Reduction of Average-Performance Degradation and Variance in Faulty CPU Cache Memories. ARCS Michail Mavropoulos, Georgios Keramidas, Dimitris Nikolos
2024	Misc	`conf`	Improving the Performance Predictability of Faulty Data Caches. EDCC Michail Mavropoulos, Georgios Keramidas, Dimitris Nikolos
2022	J	`jnl`	Enabling efficient sub-block disabled caches using coarse grain spatial predictions. Microprocess. Microsystems Michail Mavropoulos, Georgios Keramidas, Dimitris Nikolos
2021	B	`conf`	Run Time Management of Faulty Data Caches. ETS Michail Mavropoulos, Georgios Keramidas, Dimitris Nikolos
2018	A	`conf`	A novel fault tolerant cache architecture based on orthogonal latin squares theory. DATE Filippos Filippou, Georgios Keramidas, Michail Mavropoulos, Dimitris Nikolos
2016	C	`conf`	Conditional soft-edge flip-flop for SET mitigation. IOLTS Panagiotis Sismanoglou, Dimitris Nikolos
2016	—	`conf`	Low capture power dictionary-based test data compression. ISQED Panagiotis Sismanoglou, Dimitris Nikolos
2016	C	`conf`	Recovery of performance degradation in defective branch target buffers. IOLTS Filippos Filippou, Georgios Keramidas, Michail Mavropoulos, Dimitris Nikolos
2015	A	`conf`	A defect-aware reconfigurable cache architecture for low-vccmin DVFS-enabled systems. DATE Michail Mavropoulos, Georgios Keramidas, Dimitris Nikolos
2015	—	`conf`	Preemptive built-in self-test for in-field structural testing. ISQED Panagiotis Sismanoglou, Vlasis Pitsios, Dimitris Nikolos
2015	—	`conf`	Reconfigurable: Self Adaptive Fault Tolerant Cache Memory for DVS enabled Systems. ACM Great Lakes Symposium on VLSI Michail Mavropoulos, Georgios Keramidas, Grigorios Adamopoulos, Dimitris Nikolos
2014	A	`conf`	Spatial pattern prediction based management of faulty data caches. DATE Georgios Keramidas, Michail Mavropoulos, Anna Karvouniari, Dimitris Nikolos
2014	C	`conf`	Test data compression based on reuse and bit-flipping of parts of dictionary entries. DDECS Panagiotis Sismanoglou, Dimitris Nikolos
2013	—	`conf`	Enhancing dictionary based test data compression using the ATE repeat instruction. ICECS Panagiotis Sismanoglou, Dimitris Nikolos
2013	J	`jnl`	Input Test Data Compression Based on the Reuse of Parts of Dictionary Entries: Static and Dynamic Approaches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Panagiotis Sismanoglou, Dimitris Nikolos
2011	—	`conf`	Test data compression based on the reuse of parts of the dictionary entries. ICECS Panagiotis Sismanoglou, Dimitris Nikolos
2009	J	`jnl`	An Improved Search Method for Accumulator-Based Test Set Embedding. IEEE Trans. Computers Dimitris Nikolos, Dimitrios Kagaris, Samara Sudireddy, Spyros Gidaros
2009	J	`jnl`	Efficient partial scan cell gating for low-power scan-based testing. ACM Trans. Design Autom. Electr. Syst. Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
2009	A	`conf`	LFSR-based test-data compression with self-stoppable seeds. DATE M. Koutsoupia, Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos
2008	J	`jnl`	Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units. IEEE Trans. Very Large Scale Integr. Syst. Giorgos Dimitrakopoulos, Costas Galanopoulos, Christos Mavrokefalidis, Dimitris Nikolos
2008	J	`jnl`	Multilevel-Huffman Test-Data Compression for IP Cores With Multiple Scan Chains. IEEE Trans. Very Large Scale Integr. Syst. Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos
2008	J	`jnl`	Test Data Compression Based on Variable-to-Variable Huffman Encoding With Codeword Reusability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos
2007	J	`jnl`	Multilevel Huffman Coding: An Efficient Test-Data Compression Method for IP Cores. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos
2007	J	`jnl`	Optimal Selective Huffman Coding for Test-Data Compression. IEEE Trans. Computers Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos
2007	J	`jnl`	Sorter Based Permutation Units for Media-Enhanced Microprocessors. IEEE Trans. Very Large Scale Integr. Syst. Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos
2007	J	`jnl`	Testable Designs of Multiple Precharged Domino Circuits. IEEE Trans. Very Large Scale Integr. Syst. Themistoklis Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou
2006	J	`jnl`	A core generator for arithmetic cores and testing structures with a network interface. J. Syst. Archit. Dimitris Bakalis, Kostas Adaos, Dimitrios Lymperopoulos, Maciej Bellos, Haridimos T. Vergos, George Alexiou, Dimitris Nikolos
2006	—	`conf`	An Energy-Delay Efficient Subword Permutation Unit. ASAP Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos
2006	C	`conf`	Diophantine-Equation Based Arithmetic Test Set Embedding. IOLTS Dimitris Nikolos, Dimitrios Kagaris, Spyros Gidaros
2006	—	`conf`	Efficient Multiphase Test Set Embedding for Scan-based Testing. ISQED Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos
2006	A	`conf`	Efficient test-data compression for IP cores using multilevel Huffman coding. DATE Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos
2006	C	`conf`	Fast bit permutation unit for media enhanced microprocessors. ISCAS Giorgos Dimitrakopoulos, Christos Mavrokefalidis, Costas Galanopoulos, Dimitris Nikolos
2006	J	`jnl`	On Obtaining Maximum-Length Sequences for Accumulator-Based Serial TPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dimitrios Kagaris, P. Karpodinis, Dimitris Nikolos
2005	—	`conf`	Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing. PATMOS Giorgos Dimitrakopoulos, Dimitris Nikolos
2005	Misc	`conf`	Deterministic Test Vector Compression / Decompression Using an Embedded Processor. EDCC Maciej Bellos, Dimitris Nikolos
2005	J	`jnl`	Efficient Diminished-1 Modulo 2^n+1 Multipliers. IEEE Trans. Computers Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos
2005	J	`jnl`	High-Speed Parallel-Prefix VLSI Ling Adders. IEEE Trans. Computers Giorgos Dimitrakopoulos, Dimitris Nikolos
2005	—	`conf`	New architectures for modulo 2N - 1 adders. ICECS Giorgos Dimitrakopoulos, Dimitris G. Nikolos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
2005	—	`conf`	Power aware test-data compression for scan-based testing. ICECS George Gekas, Dimitris Nikolos, Emmanouil Kalligeros, Xrysovalantis Kavousianos
2005	—	`conf`	Reseeding-Based Test Set Embedding with Reduced Test Sequences. ISQED Emmanouil Kalligeros, D. Kaseridis, Xrysovalantis Kavousianos, Dimitris Nikolos
2004	—	`conf`	A new test pattern generator for high defect coverage in a BIST environment. ACM Great Lakes Symposium on VLSI Costas Laoudias, Dimitris Nikolos
2004	C	`conf`	Accumulator based Test-per-Scan BIST. IOLTS P. Karpodinis, Dimitri Kagaris, Dimitris Nikolos
2004	—	`conf`	An Efficient Test Vector Ordering Method for Low Power Testing. ISVLSI Xrysovalantis Kavousianos, Dimitris Bakalis, Maciej Bellos, Dimitris Nikolos
2004	—	`conf`	Design of High-Speed Low-Power Parallel-Prefix VLSI Adders. PATMOS Giorgos Dimitrakopoulos, Pavlos Kolovos, P. Kalogerakis, Dimitris Nikolos
2004	J	`jnl`	Fast Parallel-Prefix Modulo 2^n+1 Adders. IEEE Trans. Computers Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
2004	—	`conf`	Low Power Testing by Test Vector Ordering with Vector Repetition. ISQED Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos, Xrysovalantis Kavousianos
2004	J	`jnl`	Modified Booth Modulo 2 IEEE Trans. Computers Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
2004	J	`jnl`	Multiphase BIST: a new reseeding technique for high test-data compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos
2004	—	`conf`	Scan Cell Ordering for Low Power BIST. ISVLSI Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos
2003	—	`conf`	A Family of Parallel-Pre.x Modulo 2n - 1 Adders. ASAP Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
2003	—	`conf`	A highly regular multi-phase reseeding technique for scan-based BIST. ACM Great Lakes Symposium on VLSI Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos
2003	—	`conf`	A systematic methodology for designing area-time efficient parallel-prefix modulo 2 ISCAS (5) Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
2003	C	`conf`	An Efficient BIST scheme for High-Speed Adders. IOLTS Dimitris G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou
2003	C	`conf`	DV-TSE: Difference Vector Based Test Set Embedding. VLSI-SOC Maciej Bellos, Xrysovalantis Kavousianos, Dimitris Nikolos, Dimitri Kagaris
2003	J	`jnl`	Deterministic BIST for RNS Adders. IEEE Trans. Computers Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou
2003	—	`conf`	Efficient BIST schemes for RNS datapaths. ISCAS (5) Dimitris G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou
2003	—	`conf`	Efficient modulo 2 ICECS Costas Efstathiou, Haridimos T. Vergos, Giorgos Dimitrakopoulos, Dimitris Nikolos
2003	—	`conf`	Low Power Test Set Embedding Based on Phase Shifters. ISVLSI Maciej Bellos, Dimitri Kagaris, Dimitris Nikolos
2003	J	`jnl`	Modulo 2n±1 Adder Design Using Select-Prefix Blocks. IEEE Trans. Computers Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
2003	—	`conf`	Virtual-scan: a novel approach for software-based self-testing of microprocessors. ISCAS (5) Giorgos Dimitrakopoulos, Xrysovalantis Kavousianos, Dimitris Nikolos
2002	—	`conf`	A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing. IOLTW Y. Tsiatouhas, Angela Arapoyanni, Dimitris Nikolos, Th. Haniotakis
2002	—	`conf`	A ROMless LFSR Reseeding Scheme for Scan-based BIST. Asian Test Symposium Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos
2002	J	`jnl`	A new built-in TPG method for circuits with random patternresistant faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos, Spyros Tragoudas
2002	J	`jnl`	A new technique for IDDQ testing in nanometer technologies. Integr. Y. Tsiatouhas, Yiannis Moisiadis, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni
2002	—	`conf`	An Efficient Seeds Selection Method for LFSR-Based Test-per-Clock BIST. ISQED Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
2002	—	`conf`	Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register. IOLTW Giorgos Dimitrakopoulos, Dimitris Nikolos, Dimitris Bakalis
2002	J	`jnl`	Diminished-One Modulo 2 IEEE Trans. Computers Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos
2002	—	`conf`	Extending the Viability of IDDQ Testing in the Deep Submicron Era. ISQED Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni
2002	J	`jnl`	Guest Editorial. J. Electron. Test. Dimitris Nikolos, John P. Hayes, Michael Nicolaidis, Cecilia Metra
2002	—	`conf`	Ling adders in CMOS standard cell technologies. ICECS Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
2002	J	`jnl`	On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation. J. Syst. Archit. Dimitris Bakalis, Emmanouil Kalligeros, Dimitris Nikolos, Haridimos T. Vergos, George Alexiou
2002	J	`jnl`	On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST. J. Electron. Test. Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
2002	Misc	`conf`	Test Set Embedding Based on Phase Shifters. EDCC Maciej Bellos, Dimitrios Kagaris, Dimitris Nikolos
2001	—	`conf`	A Formal Test Set for RNS Adders and an Efficient Low Power BIST Scheme. LATW Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou
2001	—	`conf`	A New Reseeding Technique for LFSR-Based Test Pattern Generation. IOLTW Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
2001	—	`conf`	A novel reseeding technique for accumulator-based test pattern generation. ACM Great Lakes Symposium on VLSI Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
2001	—	`conf`	Concurrent Detection of Soft Errors Based on Current Monitoring. IOLTW Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Costas Efstathiou
2001	C	`conf`	EUDOXUS: A WWW-based Generator of Reusable Arithmetic Cores. IEEE International Workshop on Rapid System Prototyping Dimitris Bakalis, Kostas Adaos, George Alexiou, Dimitris Nikolos, Dimitrios Lymperopoulos
2001	C	`conf`	High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands. IEEE Symposium on Computer Arithmetic Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou
2001	J	`jnl`	Low Power Built-In Self-Test Schemes for Array and Booth Multipliers. VLSI Design Dimitris Bakalis, Xrysovalantis Kavousianos, Haridimos T. Vergos, Dimitris Nikolos, G. Ph. Alexiou
2001	—	`conf`	On Accumulator-Based Bit-Serial Test Response Compaction Schemes. ISQED Dimitris Bakalis, Dimitris Nikolos, Haridimos T. Vergos, Xrysovalantis Kavousianos
2001	—	`conf`	On the design of modulo 2 ICECS Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos
2000	—	`conf`	A Compact Built-In Current Sensor for IDDQ Testing. IOLTW Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos
2000	A	`conf`	A Versatile Built-In Self-Test Scheme for Delay Fault Testing. DATE Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni, Dimitris Nikolos
2000	J	`jnl`	High-Speed Parallel-Prefix Modulo 2n-1 Adders. IEEE Trans. Computers Lampros Kalampoukas, Dimitris Nikolos, Costas Efstathiou, Haridimos T. Vergos, John Kalamatianos
2000	—	`conf`	Low Power BIST for Wallace Tree-Based Fast Multipliers. ISQED Dimitris Bakalis, Dimitris Nikolos, George Alexiou, Emmanouil Kalligeros, Haridimos T. Vergos
2000	J	`jnl`	Novel Single and Double Output TSC CMOS Checkers for VLSI Design Xrysovalantis Kavousianos, Dimitris Nikolos, G. Sidiropoulos
2000	—	`conf`	On Testability of Multiple Precharged Domino Logic. ISQED Th. Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou
2000	A	`conf`	Test response compaction by an accumulator behaving as a multiple input non-linear feedback shift register. ITC Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
1999	J	`jnl`	An Accumulator-Based BIST Approach for Two-Pattern Testing. J. Electron. Test. Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantin Halatsis
1999	—	`conf`	Design and Analysis of On-Chip CPU Pipelined Caches. VLSI C. Ninos, Haridimos T. Vergos, Dimitris Nikolos
1999	C	`conf`	Development of a Reusable E1 Transceiver Suitable for Rapid Prototyping. IEEE International Workshop on Rapid System Prototyping A. Vasilliou, Konstantinos Gounaris, Kostas Adaos, D. Mitsainas, George Alexiou, Dimitris Nikolos
1999	—	`conf`	Easily Path Delay Fault Testable Non-Restoring Cellular Array Dividers. Asian Test Symposium G. Sidiropoulos, Haridimos T. Vergos, Dimitris Nikolos
1999	—	`conf`	Low Power Dissipation in BIST Schemes for Modified Booth Multipliers. DFT Xrysovalantis Kavousianos, Dimitris Bakalis, Haridimos T. Vergos, Dimitris Nikolos, George Alexiou
1999	Misc	`conf`	Modular TSC Checkers for Bose-Lin and Bose Codes. VTS Xrysovalantis Kavousianos, Dimitris Nikolos
1999	J	`jnl`	New efficient totally self-checking Berger code checkers. Integr. Xrysovalantis Kavousianos, Dimitris Nikolos, G. Foukarakis, T. Gnardellis
1999	—	`conf`	On Path Delay Fault Testing of Multiplexer - Based Shifters. Great Lakes Symposium on VLSI Haridimos T. Vergos, Dimitris Nikolos, Y. Tsiatouhas, Th. Haniotakis, Michael Nicolaidis
1999	J	`jnl`	On the Yield of VLSI Processors with On-Chip CPU Cache. IEEE Trans. Computers Dimitris Nikolos, Haridimos T. Vergos
1999	A	`conf`	Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks. DATE Dimitris Nikolos, Haridimos T. Vergos, Th. Haniotakis, Y. Tsiatouhas
1999	Misc	`conf`	Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks. EDCC Maciej Bellos, Dimitris Nikolos, Haridimos T. Vergos
1999	—	`conf`	Path delay fault testing of Benes multistage interconnection networks. ICECS Haridimos T. Vergos, Maciej Bellos, Dimitris Nikolos
1998	—	`conf`	C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications. DFT Th. Haniotakis, Dimitris Nikolos, Y. Tsiatouhas
1998	Misc	`conf`	Novel Single and Double Output TSC Berger Code Checkers. VTS Xrysovalantis Kavousianos, Dimitris Nikolos
1998	J	`jnl`	Optimal Self-Testing Embedded Parity Checkers. IEEE Trans. Computers Dimitris Nikolos
1998	A	`conf`	R-CBIST: an effective RAM-based input vector monitoring concurrent BIST technique. ITC Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantinos Halatsis
1998	J	`jnl`	Self-Testing Embedded Two-Rail Checkers. J. Electron. Test. Dimitris Nikolos
1997	—	`conf`	Design of Compact and High speed, Totally Self Checking CMOS Checkers for m-out-of-n Codes. DFT Xrysovalantis Kavousianos, Dimitris Nikolos, G. Sidiropoulos
1997	Misc	`conf`	Self-exercising self testing k-order comparators. VTS Xrysovalantis Kavousianos, Dimitris Nikolos
1996	J	`jnl`	An efficient built-in self test method for robust path delay fault testing. J. Electron. Test. Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantin Halatsis
1996	Misc	`conf`	On the Yield of VLSI Processors with on-chip CPU Cache. EDCC Dimitris Nikolos, Haridimos T. Vergos
1996	J	`jnl`	Testing CMOS combinational iterative logic arrays for realistic faults. Integr. Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis
1996	—	`conf`	Yield - Performance Tradeoffs for VLSI Processors with Partially Good Two-Level On-Chip Caches. DFT Dimitris Nikolos, Haridimos T. Vergos, Antonis Vazaios, Spyros Voulgaris
1995	—	`conf`	Accumulator-based BIST approach for stuck-open and delay fault testing. ED&TC Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantin Halatsis
1995	—	`conf`	An efficient comparative concurrent Built-In Self-Test technique. Asian Test Symposium Ioannis Voyiatzis, Dimitris Nikolos, Antonis M. Paschalis, Constantinos Halatsis, Th. Haniotakis
1995	J	`jnl`	Efficient Totally Self-Checking Checkers for a Class of Borden Codes. IEEE Trans. Computers Th. Haniotakis, Antonis M. Paschalis, Dimitris Nikolos
1995	J	`jnl`	Efficient fault tolerant cache memory design. Microprocess. Microprogramming Haridimos T. Vergos, Dimitris Nikolos
1995	J	`jnl`	On TSC Checkers for m-out-n Codes. IEEE Trans. Computers Vassilios V. Dimakopoulos, G. Sourtziotis, Antonis M. Paschalis, Dimitris Nikolos
1995	Misc	`conf`	Testing combinational iterative logic arrays for realistic faults. VTS Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis
1992	J	`jnl`	Theory and Design of t-Error Correcting, k-Error Detecting and d-Unidirectional Error Detecting Codes with d > k > t. IEEE Trans. Computers Dimitris Nikolos, Alexandros Krokos
1991	J	`jnl`	Theory and Design of t-Error Correcting/d-Error Detecting (d>t) and All Unidirectional Error Detecting Codes. IEEE Trans. Computers Dimitris Nikolos
1988	J	`jnl`	Efficient Design of Totally Self-Checking Checkers for all Low-Cost Arithmetic Codes. IEEE Trans. Computers Dimitris Nikolos, Antonis M. Paschalis, George Philokyprou
1988	J	`jnl`	Efficient Modular Design of TSC Checkers for IEEE Trans. Computers Antonis M. Paschalis, Dimitris Nikolos, Constantine Halatsis
1986	—	`conf`	Efficient Modular Design of TSC Checkers for M-out-of-2M Codes. Aegean Workshop on Computing Antonis M. Paschalis, Dimitris Nikolos, Constantine Halatsis
1986	J	`jnl`	Systematic IEEE Trans. Computers Dimitris Nikolos, Nikolaos Gaitanis, George Philokyprou
1984	—	`conf`	Systematic t-error correcting all unidirectional error detecting codes. Fehlertolerierende Rechensysteme Dimitris Nikolos, Nikolaos Gaitanis, George Philokyprou