Dimitris Bakalis

43 papers A 1C 6Journal 13Unranked 22

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Efficient modulo 2 ISVLSI Dimitris Bakalis, Haridimos T. Vergos
2015	J	`jnl`	Lookahead Architectures for Hamming Distance and Fixed-Threshold Hamming Weight Comparators. Circuits Syst. Signal Process. Haridimos T. Vergos, Dimitris Bakalis, A. Anastasiou
2013	—	`conf`	Modulo 2 EUROCON Evangelos Vassalos, Dimitris Bakalis
2013	—	`conf`	On the design of modulo 2 ACM Great Lakes Symposium on VLSI Evangelos Vassalos, Dimitris Bakalis
2013	—	`conf`	RNS assisted image filtering and edge detection. DSP Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos
2013	—	`conf`	Reverse converters for RNSs with diminished-one encoded channels. EUROCON Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos
2012	J	`jnl`	Area-time efficient multi-modulus adders and their applications. Microprocess. Microsystems Haridimos T. Vergos, Dimitris Bakalis
2012	J	`jnl`	CSD-RNS-based Single Constant Multipliers. J. Signal Process. Syst. Evangelos Vassalos, Dimitris Bakalis
2012	C	`conf`	SUT-RNS Residue-to-Binary Converters Design. DSD Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos
2011	J	`jnl`	Efficient modulo 2 Integr. Dimitris Bakalis, Haridimos T. Vergos, Anastasia Spyrou
2011	C	`conf`	Modulo 2^n+1 Arithmetic Units with Embedded Diminished-to-Normal Conversion. DSD Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos
2011	J	`jnl`	On the Design of Modulo 2 Circuits Syst. Signal Process. Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos
2011	—	`conf`	On the use of double-LSB and signed-LSB encodings for RNS. DSP Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos
2010	C	`conf`	Area-Efficient Multi-moduli Squarers for RNS. DSD Dimitris Bakalis, Haridimos T. Vergos
2010	J	`jnl`	Fast modulo 2 Integr. Haridimos T. Vergos, Dimitris Bakalis, Costas Efstathiou
2010	J	`jnl`	On Implementing Efficient Modulo 2 J. Circuits Syst. Comput. Haridimos T. Vergos, Dimitris Bakalis
2010	—	`conf`	SUT-RNS Forward and Reverse Converters. ISVLSI Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos
2010	—	`conf`	SUT-RNS Forward and Reverse Converters. ISVLSI (Selected papers) Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos
2009	C	`conf`	Combined SD-RNS Constant Multiplication. DSD Evangelos Vassalos, Dimitris Bakalis
2009	—	`conf`	Efficient architectures for modulo 2n-1 squares. DPS Anastasia Spyrou, Dimitris Bakalis, Haridimos T. Vergos
2009	J	`jnl`	Efficient partial scan cell gating for low-power scan-based testing. ACM Trans. Design Autom. Electr. Syst. Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
2009	—	`conf`	Novel modulo 2n+1 subtractors. DPS Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos
2008	—	`conf`	Efficient modulo 2 ICECS Haridimos T. Vergos, Dimitris Bakalis, Costas Efstathiou
2008	C	`conf`	On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components. DSD Haridimos T. Vergos, Dimitris Bakalis
2006	J	`jnl`	A core generator for arithmetic cores and testing structures with a network interface. J. Syst. Archit. Dimitris Bakalis, Kostas Adaos, Dimitrios Lymperopoulos, Maciej Bellos, Haridimos T. Vergos, George Alexiou, Dimitris Nikolos
2004	—	`conf`	An Efficient Test Vector Ordering Method for Low Power Testing. ISVLSI Xrysovalantis Kavousianos, Dimitris Bakalis, Maciej Bellos, Dimitris Nikolos
2004	—	`conf`	Low Power Testing by Test Vector Ordering with Vector Repetition. ISQED Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos, Xrysovalantis Kavousianos
2004	—	`conf`	Scan Cell Ordering for Low Power BIST. ISVLSI Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos
2002	J	`jnl`	A new built-in TPG method for circuits with random patternresistant faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos, Spyros Tragoudas
2002	—	`conf`	An Efficient Seeds Selection Method for LFSR-Based Test-per-Clock BIST. ISQED Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
2002	—	`conf`	Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register. IOLTW Giorgos Dimitrakopoulos, Dimitris Nikolos, Dimitris Bakalis
2002	J	`jnl`	On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation. J. Syst. Archit. Dimitris Bakalis, Emmanouil Kalligeros, Dimitris Nikolos, Haridimos T. Vergos, George Alexiou
2002	J	`jnl`	On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST. J. Electron. Test. Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
2001	—	`conf`	A New Reseeding Technique for LFSR-Based Test Pattern Generation. IOLTW Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
2001	—	`conf`	A novel reseeding technique for accumulator-based test pattern generation. ACM Great Lakes Symposium on VLSI Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
2001	C	`conf`	EUDOXUS: A WWW-based Generator of Reusable Arithmetic Cores. IEEE International Workshop on Rapid System Prototyping Dimitris Bakalis, Kostas Adaos, George Alexiou, Dimitris Nikolos, Dimitrios Lymperopoulos
2001	J	`jnl`	Low Power Built-In Self-Test Schemes for Array and Booth Multipliers. VLSI Design Dimitris Bakalis, Xrysovalantis Kavousianos, Haridimos T. Vergos, Dimitris Nikolos, G. Ph. Alexiou
2001	—	`conf`	On Accumulator-Based Bit-Serial Test Response Compaction Schemes. ISQED Dimitris Bakalis, Dimitris Nikolos, Haridimos T. Vergos, Xrysovalantis Kavousianos
2001	—	`conf`	On the Design of Self-Testing Checkers for Modified Berger Codes. IOLTW Stanislaw J. Piestrak, Dimitris Bakalis, Xrysovalantis Kavousianos
2001	—	`—`	Δομές ενσωματωμένου αυτοελέγχου για ψηφιακά κυκλώματα πολύ μεγάλης κλίμακας ολοκλήρωσης Dimitris Bakalis
2000	—	`conf`	Low Power BIST for Wallace Tree-Based Fast Multipliers. ISQED Dimitris Bakalis, Dimitris Nikolos, George Alexiou, Emmanouil Kalligeros, Haridimos T. Vergos
2000	A	`conf`	Test response compaction by an accumulator behaving as a multiple input non-linear feedback shift register. ITC Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
1999	—	`conf`	Low Power Dissipation in BIST Schemes for Modified Booth Multipliers. DFT Xrysovalantis Kavousianos, Dimitris Bakalis, Haridimos T. Vergos, Dimitris Nikolos, George Alexiou