Dimitrios Velenis

44 papers A 1B 2C 4Misc 1Journal 7Unranked 29

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	110 GHz GeSi Electroabsorption Modulator on a 300mm SiPh Platform Enabling High-Density 400G/lane IM/DO Links. ECOC Cedric Bruynsteen, Zohauddin Ahmad, Leandro da Silva, Minkyu Kim, Conor Coughlan, Dharmander Malik, Mathias Berciano, Guy Lepage, Roger Loo, Hakim Kobbi, Huseyin Sar, Swetanshu Bipul, Chiara Marchese, Peter Verheyen, Peter De Heyn, Dimitrios Velenis, Maumita Chakrabarti, Filippo Ferraro, Yoojin Ban, Nishant Singh, Peter Ossieur, Joris Van Campenhout
2025	—	`conf`	320 Gb/s Unamplified Transmission Using 1 00 GHz Ge PD and TFLN MZM on a Foundry-Compatible SiPh Platform Co-Packaged with Traveling-Wave Drivers and TIAs. ECOC Jakob Declercq, Shengpu Niu, Margot Niels, Amir Shahin, Joris Van Kerrebrouck, Maximilien Billet, Mathias Berclano, Joris Lambrecht, Bart Moeneclaey, Tom Vanackere, Ewoud Vissers, Conor Coughlan, Gunther Roelkens, Arno Moerman, Olivier Caytan, Sam Lemey, Maumita Chakrabarti, Hakim Kobbi, Minkyu Kim, Didit Yudistira, Roger Loo, Swetanshu Bipul, Filippo Ferraro, Yoojin Ban, Peter De Heyn, Guy Torfs, Johan Bauwelinck, Dimitrios Velenis, Peter Ossieur, Philippe Absil, Bart Kuyken, Joris Van Campenhout, Nishant Singh, Cedric Bruynsteen, Xin Yin
2025	—	`conf`	70 GHz, 2 A/W, Waveguide-Coupled Germanium-in-Silicon Avalanche Photodiode. ECOC Amir Shahin, Conor Coughlan, Mathias Berciano, Didit Yudistira, Shuchi Kaushik, Roger Loo, Hakim Kobbi, Patrick Carolan, Marta Agati, Dries Van Thourhout, Peter Verheyen, Maumita Chakrabarti, Yoojin Ban, Dimitrios Velenis, Filippo Ferraro, Joris Van Campenhout
2025	—	`conf`	A 50 Gb/S NRZ O-Band Silicon Disk Modulator with 6.4 THz FSR. ECOC Minkyu Kim, Chiara Marchese, Rafal Magdziak, Hakim Kobbi, Peter De Heyn, Dimitrios Velenis, Filippo Ferraro, Yoojin Ban, Joris Van Campenhout
2025	—	`conf`	Ultra-compact silicon rings with high thermal tuning efficiency demonstrated as an 8×400 GHz WDM filter. OFC Qingzhong Deng, Jeroen De Coster, Rafal Magdziak, Ahmed H. El-Saeed, Alaa Elshazly, Mehmet Oktay, Chiara Marchese, Guy Lepage, Javad Rahimi Vaskasi, Sadhishkumar Balakrishnan, Neha Singh, Dieter Bode, Marko Ersek Filipcic, Maumita Chakrabarti, Dimitrios Velenis, Peter Verheyen, Philippe Absil, Filippo Ferraro, Yoojin Ban, Joris Van Campenhout
2024	—	`conf`	32×100 GHz WDM filter based on ultra-compact silicon rings with a high thermal tuning efficiency of 5.85 mW/π. OFC Qingzhong Deng, Ahmed H. El-Saeed, Alaa Elshazly, Guy Lepage, Chiara Marchese, Hakim Kobbi, Rafal Magdziak, Jeroen De Coster, Neha Singh, Marko Ersek Filipcic, Kristof Croes, Dimitrios Velenis, Maumita Chakrabarti, Peter De Heyn, Peter Verheyen, Philippe Absil, Filippo Ferraro, Yoojin Ban, Joris Van Campenhout
2024	—	`conf`	Collective die-to-wafer bonding enabling low-loss evanescent coupling for optically interconnected System-on-Wafer. OFC Pengfei Xu, Junwen He, Koen Kennes, Anton Dvoretskii, Arnita Podpod, Guy Lepage, Negin Golshani, Rafal Magdziak, Swetanshu Bipul, Dieter Bode, Peter Verheyen, Maumita Chakrabarti, Dimitrios Velenis, Andy Miller, Yoojin Ban, Filippo Ferraro, Joris Van Campenhout
2024	—	`conf`	Low-loss, multi-reticle stitched SiN waveguides for 300mm wafer-level optical interconnects. OFC Pengfei Xu, Chiara Marchese, Guy Lepage, Negin Golshani, Ruben Van Eenaeme, Andrea Mingardi, Joost Van Ongeval, Rafal Magdziak, Luc Halipre, Darko Trivkovic, Peter Verheyen, Maumita Chakrabarti, Dimitrios Velenis, Andy Miller, Filippo Ferraro, Yoojin Ban, Joris Van Campenhout
2023	—	`conf`	Highly Optimized O-band Si Ring Modulators for Low-Power Hybrid CMOS-SiPho Transceivers. OFC Yoojin Ban, Minkyu Kim, Peter De Heyn, Davide Guermandi, Filippo Ferraro, Natarajan Rajasekaran, Peter Verheyen, Pieter Bex, Junwen He, Hakim Kobbi, Jeroen De Coster, Rafal Magdziak, Dieter Bode, Sebastien Lardenois, Nicolas Pantano, Dimitrios Velenis, Joris Van Campenhout
2022	—	`conf`	(Why do we need) Wireless Heterogeneous Integration (anyway?). VLSI Technology and Circuits Michaël Peeters, S. Sinha, Xiao Sun, Claude Desset, Giuseppe Gramegna, John Slabbekoorn, Pieter Bex, Nelson Pinho, Tomas Webers, Dimitrios Velenis, Andy Miller, Nadine Collaert, Geert Van der Plas, Eric Beyne, Martijn Huynen, R. Broucke
2022	J	`jnl`	84%-Efficiency Fully Integrated Voltage Regulator for Computing Systems Enabled by 2.5-D High-Density MIM Capacitor. IEEE Trans. Very Large Scale Integr. Syst. Hesheng Lin, Dimitrios Velenis, Philip Nolmans, Xiao Sun, Francky Catthoor, Rudy Lauwereins, Geert Van der Plas, Eric Beyne
2022	J	`jnl`	Efficient Backside Power Delivery for High-Performance Computing Systems. IEEE Trans. Very Large Scale Integr. Syst. Hesheng Lin, Geert Van der Plas, Xiao Sun, Dimitrios Velenis, Francky Catthoor, Rudy Lauwereins, Eric Beyne
2021	—	`conf`	110GHz Through-Silicon Via's Integrated in Silicon Photonics Interposers for Next-Generation Optical Modules. ECOC Kenichi Miyaguchi, Yoojin Ban, Nicolas Pantano, Xiao Sun, Philippe Absil, Lieve Bogaerts, Peter Verheyen, Dimitrios Velenis, Marianna Pantouvaki, Joris Van Campenhout
2019	J	`jnl`	Fabrication Cost Analysis for Contactless 3-D ICs. IEEE Trans. Circuits Syst. II Express Briefs Ioannis A. Papistas, Vasilis F. Pavlidis, Dimitrios Velenis
2019	—	`conf`	Process Complexity and Cost Considerations of Multi-Layer Die Stacks. 3DIC Dimitrios Velenis, Joeri De Vos, Soon-Wook Kim, Jaber Derakhshandeh, Pieter Bex, Giovanni Capuz, Samuel Suhard, Kenneth June Rebibis, Stefaan Van Huylenbroeck, Erik Jan Marinissen, Alain Phommahaxay, Andy Miller, Gerald Beyer, Geert Van der Plas, Eric Beyne
2019	—	`conf`	Study of the Mechanical Stress Impact on Silicide Contact Resistance by 4-Point Bending. IRPS Yefan Liu, Hao Yu, Gaspard Hiblot, Anastasiia Kruv, Marc Schaekers, Naoto Horiguchi, Dimitrios Velenis, Ingrid De Wolf
2015	—	`conf`	Active-lite interposer for 2.5 & 3D integration. VLSIC Geert Hellings, Mirko Scholz, Mikael Detalle, Dimitrios Velenis, Muriel de Potter de ten Broeck, C. Roda Neve, Y. Li, Stefaan Van Huylenbroeck, Shih-Hung Chen, Erik Jan Marinissen, Antonio La Manna, Geert Van der Plas, Dimitri Linten, Eric Beyne, Aaron Thean
2015	—	`conf`	Processing active devices on Si interposer and impact on cost. 3DIC Dimitrios Velenis, Mikael Detalle, Geert Hellings, Mirko Scholz, Erik Jan Marinissen, Geert Van der Plas, Antonio La Manna, Andy Miller, Dimitri Linten, Eric Beyne
2013	—	`conf`	Si interposer build-up options and impact on 3D system cost. 3DIC Dimitrios Velenis, Mikael Detalle, Erik Jan Marinissen, Eric Beyne
2012	J	`jnl`	Capacitance Measurements of Two-Dimensional and Three-Dimensional IC Interconnect Structures by Quasi-Static C-V Technique. IEEE Trans. Instrum. Meas. Michele Stucchi, Dimitrios Velenis, Guruprasad Katti
2011	—	`conf`	3D stacking using ultra thin dies. 3DIC Antonio La Manna, Dimitrios Velenis, Thibault Buisson, Mikael Detalle, Kenneth J. Rebibis, Wenqi Zhang, Eric Beyne
2011	J	`jnl`	Design Issues and Considerations for Low-Cost 3-D TSV IC Technology. IEEE J. Solid State Circuits Geert Van der Plas, Paresh Limaye, Igor Loi, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Antonio Pullini, Federico Angiolini, Luca Benini, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal
2011	—	`conf`	Development of cost-effective biocompatible packaging for microelectronic devices. EMBC Karen Qian, Karl Malachowski, Paolo Fiorini, Dimitrios Velenis, Maaike Op de Beeck, Chris Van Hoof
2010	C	`conf`	3D integration: Circuit design, test, and reliability challenges. IOLTS Nikolaos Minas, Ingrid De Wolf, Erik Jan Marinissen, Michele Stucchi, Herman Oprins, Abdelkarim Mercha, Geert Van der Plas, Dimitrios Velenis, Pol Marchal
2010	—	`conf`	Cost effectiveness of 3D integration options. 3DIC Dimitrios Velenis, Erik Jan Marinissen, Eric Beyne
2010	—	`conf`	Design issues and considerations for low-cost 3D TSV IC technology. ISSCC Geert Van der Plas, Paresh Limaye, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Domae Shinichi, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Wim Dehaene, Youssef Travaly, Pol Marchal, Eric Beyne
2010	B	`conf`	On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking. ETS Jouke Verbree, Erik Jan Marinissen, Philippe Roussel, Dimitrios Velenis
2009	J	`jnl`	Effects of Parameter Variations on Timing Characteristics of Clocked Registers. J. Circuits Syst. Comput. William R. Roberts, Dimitrios Velenis
2009	—	`conf`	Impact of 3D design choices on manufacturing cost. 3DIC Dimitrios Velenis, Michele Stucchi, Erik Jan Marinissen, Bart Swinnen, Eric Beyne
2007	C	`conf`	Efficient Insertion of Crosstalk Shielding along On-Chip Interconnect Trees. ISCAS Boyan Semerdjiev, Dimitrios Velenis
2007	Misc	`conf`	Optimal Crosstalk Shielding Insertion along On-Chip Interconnect Trees. VLSI Design Boyan Semerdjiev, Dimitrios Velenis
2006	—	`conf`	Effects of Parameter Variations and Crosstalk Noise on H-Tree Clock Distribution Networks. ISVLSI Itisha Chanodia, Dimitrios Velenis
2006	C	`conf`	Effects of crosstalk noise on H-tree clock distribution networks. ISCAS Itisha Chanodia, Dimitrios Velenis
2006	—	`conf`	Effects of process and environmental variations on timing characteristics of clocked registers. ACM Great Lakes Symposium on VLSI William R. Roberts, Dimitrios Velenis
2006	C	`conf`	Power supply variation effects on timing characteristics of clocked registers. ISCAS William R. Roberts, Dimitrios Velenis
2005	—	`conf`	Parameter Variation Effects on Timing Characteristics of High Performance Clocked Registers. PATMOS William R. Roberts, Dimitrios Velenis
2004	—	`conf`	Buffer Sizing for Crosstalk Induced Delay Uncertainty. PATMOS Dimitrios Velenis, Eby G. Friedman
2004	—	`conf`	Buffer sizing for delay uncertainty induced by process variations. ICECS Dimitrios Velenis, Ramyashree Sundaresha, Eby G. Friedman
2004	—	`conf`	Clock tree layout design for reduced delay uncertainty. SoCC Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman
2003	A	`conf`	Reduced Delay Uncertainty in High Performance Clock Distribution Networks. DATE Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman
2002	J	`jnl`	Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling. J. Circuits Syst. Comput. Dimitrios Velenis, Kevin T. Tang, Ivan S. Kourtev, Victor Adler, Franklin Baez, Eby G. Friedman
2002	B	`conf`	SaTPEP: A TCP Performance Enhancing Proxy for Satellite Links. NETWORKING Dimitrios Velenis, Dimitrios Kalogeras, Basil S. Maglaris
2001	—	`conf`	A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty. ISCAS (4) Dimitrios Velenis, Eby G. Friedman, Marios C. Papaefthymiou
2001	—	`conf`	Demonstration of speed enhancements on an industrial circuit through application of non-zero clock skew scheduling. ICECS Dimitrios Velenis, Kevin T. Tang, Ivan S. Kourtev, Victor Adler, Franklin Baez, Eby G. Friedman