Dimitrios Stathis

37 papers A* 1A 2B 1C 4Misc 1Journal 15Unranked 12

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	SIMBRAIN: A nonidealities-aware simulation framework for spiking neural networks based on memristor crossbars. Neurocomputing Jiawei Xu, Yi Zheng, Ruisi Shen, Ruijia Wang, Jie Li, Deyu Wang, Dimitrios Stathis, Lirong Zheng, Zhuo Zou, Ahmed Hemani
2025	J	`jnl`	MemMIMO: A Simulation Framework for Memristor-Based Massive MIMO Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jiawei Xu, Yi Zheng, Dimitrios Stathis, Ruijia Wang, Ruisi Shen, Lirong Zheng, Zhuo Zou, Ahmed Hemani
2025	J	`jnl`	Scalable Multi-FPGA HPC Architecture for Associative Memory System. IEEE Trans. Biomed. Circuits Syst. Deyu Wang, Xiaoze Yan, Yu Yang, Dimitrios Stathis, Ahmed Hemani, Anders Lansner, Jiawei Xu, Li-Rong Zheng, Zhuo Zou
2024	J	`jnl`	Application Level Synthesis: Creating Matrix-Matrix Multiplication Library: A Case Study. IEEE Access Pudi Dhilleswararao, Yu Yang, Dimitrios Stathis, Sunil Kumar Prajapati, Srinivas Boppu, Ahmed Hemani, Linga Reddy Cenkeramaddi
2024	C	`conf`	Exploration of Custom Floating-Point Formats: A Systematic Approach. DSD Saba Yousefzadeh, Yu Yang, Astile Peter, Dimitrios Stathis, Ahmed Hemani
2024	B	`conf`	FPGA-Based HPC for Associative Memory System. ASPDAC Deyu Wang, Yuning Wang, Yu Yang, Dimitrios Stathis, Ahmed Hemani, Anders Lansner, Jiawei Xu, Li-Rong Zheng, Zhuo Zou
2024	J	`jnl`	Modeling Cycle-to-Cycle Variation in Memristors for In-Situ Unsupervised Trace-STDP Learning. IEEE Trans. Circuits Syst. II Express Briefs Jiawei Xu, Yi Zheng, Feng Li, Dimitrios Stathis, Ruisi Shen, Haoming Chu, Anders Lansner, Lirong Zheng, Zhuo Zou, Ahmed Hemani
2023	J	`jnl`	A Memristor-Based Learning Engine for Synaptic Trace-Based Online Learning. IEEE Trans. Biomed. Circuits Syst. Deyu Wang, Jiawei Xu, Feng Li, Lianhao Zhang, Chengwei Cao, Dimitrios Stathis, Anders Lansner, Ahmed Hemani, Lirong Zheng, Zhuo Zou
2023	J	`jnl`	Clock tree generation by abutment in synchoros VLSI design. Microprocess. Microsystems Dimitrios Stathis, Panagiotis Chaourani, Syed M. A. H. Jafri, Ahmed Hemani
2023	Misc	`conf`	DRRA-based Reconfigurable Architecture for Mixed-Radix FFT. VLSID Reeshita Kallapu, Dimitrios Stathis, Srinivas Boppu, Ahmed Hemani
2023	—	`conf`	Optimizing Self-Organizing Maps for Bacterial Genome Identification on Parallel Ultra-Low-Power Platforms. ICECS Seyed Ahmad Mirsalari, Saba Yousefzadeh, Giuseppe Tagliavini, Dimitrios Stathis, Ahmed Hemani
2023	—	`conf`	Optoelectronic Memristor Model for Optical Synaptic Circuit of Spiking Neural Networks. NEWCAS Jiawei Xu, Yi Zheng, Chenxu Sheng, Yichen Cai, Dimitrios Stathis, Ruisi Shen, Lirong Zheng, Zhuo Zou, Laigui Hu, Ahmed Hemani
2022	J	`jnl`	MOHAQ: Multi-Objective Hardware-Aware Quantization of recurrent neural networks. J. Syst. Archit. Nesma M. Rezk, Tomas Nordström, Dimitrios Stathis, Zain Ul-Abdin, Eren Erdal Aksoy, Ahmed Hemani
2022	A	`conf`	Reducing the Configuration Overhead of the Distributed Two-level Control System. DATE Yu Yang, Dimitrios Stathis, Ahmed Hemani
2022	—	`—`	Synchoros VLSI Design Style. Dimitrios Stathis
2021	—	`conf`	A Memristor Model with Concise Window Function for Spiking Brain-Inspired Computation. AICAS Jiawei Xu, Deyu Wang, Feng Li, Lianhao Zhang, Dimitrios Stathis, Yu Yang, Yi Jin, Anders Lansner, Ahmed Hemani, Zhuo Zou, Li-Rong Zheng
2021	A	`conf`	Approximate computation of post-synaptic spikes reduces bandwidth to synaptic storage in a model of cortex. DATE Dimitrios Stathis, Yu Yang, Ahmed Hemani, Anders Lansner
2021	—	`conf`	Clock Tree Generation by Abutment in Synchoros VLSI Design. NorCAS Dimitrios Stathis, Panagiotis Chaourani, Syed M. A. H. Jafri, Ahmed Hemani
2021	—	`conf`	Design and Implementation of Optimized Register File for Streaming Applications. VDAT Ayazulla Khan Patan, Dimitrios Stathis, Pudi Dhilleswararao, Yu Yang, Srinivas Boppu, Ahmed Hemani
2021	J	`jnl`	Multi-objective Recurrent Neural Networks Optimization for the Edge - a Quantization-based Approach. CoRR Nesma M. Rezk, Tomas Nordström, Dimitrios Stathis, Zain Ul-Abdin, Eren Erdal Aksoy, Ahmed Hemani
2021	J	`jnl`	Synthesis of Predictable Global NoC by Abutment in Synchoros VLSI Design. CoRR Jordi Altayó González, Dimitrios Stathis, Ahmed Hemani
2021	—	`conf`	Synthesis of predictable global NoC by abutment in synchoros VLSI design. NOCS Jordi Altayó González, Dimitrios Stathis, Ahmed Hemani
2020	A*	`conf`	NACU: A Non-Linear Arithmetic Unit for Neural Networks. DAC Guido Baccelli, Dimitrios Stathis, Ahmed Hemani, Maurizio Martina
2020	J	`jnl`	eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex. J. Signal Process. Syst. Dimitrios Stathis, Chirag Sudarshan, Yu Yang, Matthias Jung, Christian Weis, Ahmed Hemani, Anders Lansner, Norbert Wehn
2019	—	`conf`	Approximate Computing Applied to Bacterial Genome Identification using Self-Organizing Maps. ISVLSI Dimitrios Stathis, Yu Yang, Saurabh Tewari, Ahmed Hemani, Kolin Paul, Manfred G. Grabherr, Rafi Ahmad
2019	J	`jnl`	Regional Clock Tree Generation by Abutment in Synchoros VLSI Design. CoRR Dimitrios Stathis, Panagiotis Chaourani, Syed M. A. H. Jafri, Ahmed Hemani
2019	J	`jnl`	eBrainII: A 3 kW Realtime Custom 3D DRAM integrated ASIC implementation of a Biologically Plausible Model of a Human Scale Cortex. CoRR Dimitrios Stathis, Chirag Sudarshan, Yu Yang, Matthias Jung, Syed Mohammad Asad Hassan Jafri, Christian Weis, Ahmed Hemani, Anders Lansner, Norbert Wehn
2018	J	`jnl`	Massively Parallel Analog Computing: Ariadne's Thread Was Made of Memristors. IEEE Trans. Emerg. Top. Comput. Ioannis Vourkas, Dimitrios Stathis, Georgios Ch. Sirakoulis
2018	—	`conf`	RiBoSOM: rapid bacterial genome identification using self-organizing map implemented on the synchoros SiLago platform. SAMOS Yu Yang, Dimitrios Stathis, Prashant Sharma, Kolin Paul, Ahmed Hemani, Manfred G. Grabherr, Rafi Ahmad
2017	—	`conf`	Can a reconfigurable architecture beat ASIC as a CNN accelerator? SAMOS Syed M. A. H. Jafri, Ahmed Hemani, Dimitrios Stathis
2017	—	`conf`	MTP-Caffe: Memory, Timing, and Power aware tool for mapping CNNs to GPUs. PARMA-DITAM@HiPEAC Yu Yang, Syed M. A. H. Jafri, Ahmed Hemani, Dimitrios Stathis
2016	J	`jnl`	Alternative Architectures Toward Reliable Memristive Crossbar Memories. IEEE Trans. Very Large Scale Integr. Syst. Ioannis Vourkas, Dimitrios Stathis, Georgios Ch. Sirakoulis, Said Hamdioui
2015	C	`conf`	Live demonstration: XbarSim: An educational simulation tool for memristive crossbar-based circuits. ISCAS Ioannis Vourkas, Dimitrios Stathis, Georgios Ch. Sirakoulis
2015	C	`conf`	XbarSim: An educational simulation tool for memristive crossbar-based circuits. ISCAS Ioannis Vourkas, Dimitrios Stathis, Georgios Ch. Sirakoulis
2014	—	`conf`	Shortest Path Computing Using Memristor-Based Circuits and Cellular Automata. ACRI Dimitrios Stathis, Ioannis Vourkas, Georgios Ch. Sirakoulis
2014	—	`conf`	Solving AI problems with memristors: A case study for optimal "bin packing". Panhellenic Conference on Informatics Dimitrios Stathis, Ioannis Vourkas, Georgios Ch. Sirakoulis
2013	C	`conf`	Improved read voltage margins with alternative topologies for memristor-based crossbar memories. VLSI-SoC Ioannis Vourkas, Dimitrios Stathis, Georgios Ch. Sirakoulis