Dimin Niu

75 papers A* 18A 10B 1C 2Journal 27Unranked 16
YearRankTypeTitle / Venue / Authors
2026 J jnl
A Flexible Zero-Shot Approach to Tone Mapping via Structure-Preserving Diffusion Models.
IEEE Trans. Circuits Syst. Video Technol.
Ruoxi Zhu, Shusong Xu, Peiye Liu, Jiaming Liu, Yanheng Lu, Dimin Niu, Hongzhong Zheng, Yen-Kuang Chen, Ming-e Jing, Yibo Fan
2026 J jnl
Closely-Coupled Reconstruction and Generation for Blind Face Restoration.
IEEE Trans. Multim.
Shichen Peng, Jiaming Liu, Zihao Liu, Hongzhong Zheng, Dimin Niu, Xiaoyang Zeng, Yibo Fan
2026 J jnl
STEED: Space and Time-Efficient Encrypted Database Using FHE.
IEEE Trans. Dependable Secur. Comput.
Fahong Zhang, Zhen Gu, Yiran Li, Yilei Wang, Cheng Hong, Zhaohui Chen, Yufei Wang, Yanheng Lu, Meng Li, Leibo Liu, Sheng Wang, Feifei Li, Chen Yang, Dimin Niu, Yuan Xie
2025 J jnl
A Tightly Coupled AI-ISP Vision Processor.
IEEE Trans. Circuits Syst. Video Technol.
Hao Zhang, Sicheng Li, Yupeng Gui, Zhiyong Li, Shusong Xu, Yanheng Lu, Dimin Niu, Hongzhong Zheng, Yen-Kuang Chen, Yuan Xie, Yibo Fan
2025 — conf
CTXNL: A Software-Hardware Co-designed Solution for Efficient CXL-Based Transaction Processing.
ASPLOS (2)
Zhao Wang, Yiqi Chen, Cong Li, Yijin Guan, Dimin Niu, Tianchan Guan, Zhaoyang Du, Xingda Wei, Guangyu Sun
2025 J jnl
Enabling Efficient Transaction Processing on CXL-Based Memory Sharing.
CoRR
Zhao Wang, Yiqi Chen, Cong Li, Dimin Niu, Tianchan Guan, Zhaoyang Du, Xingda Wei, Guangyu Sun
2025 A* conf
Frequency-Biased Synergistic Design for Image Compression and Compensation.
CVPR
Jiaming Liu, Qi Zheng, Zihao Liu, Yilian Zhong, Peiye Liu, Tao Liu, Shusong Xu, Yanheng Lu, Sicheng Li, Dimin Niu, Yibo Fan
2025 A* conf
H
ISCA
Cong Li, Yihan Yin, Xintong Wu, Jingchen Zhu, Zhutianya Gao, Dimin Niu, Qiang Wu, Xin Si, Yuan Xie, Chen Zhang, Guangyu Sun
2025 A conf
HD-MoE: Hybrid and Dynamic Parallelism for Mixture-of-Expert LLMs with 3D Near-Memory Processing.
ICCAD
Haochen Huang, Shuzhang Zhong, Zhe Zhang, Shuangchen Li, Dimin Niu, Hongzhong Zheng, Runsheng Wang, Meng Li
2025 J jnl
HD-MoE: Hybrid and Dynamic Parallelism for Mixture-of-Expert LLMs with 3D Near-Memory Processing.
CoRR
Haochen Huang, Shuzhang Zhong, Zhe Zhang, Shuangchen Li, Dimin Niu, Hongzhong Zheng, Runsheng Wang, Meng Li
2025 J jnl
Matrix: Multi-Cipher Structures Dataflow for Parallel and Pipelined TFHE Accelerator.
ACM Trans. Archit. Code Optim.
Ling Liang, Zhen Gu, Fahong Zhang, Zhaohui Chen, Zhirui Li, Xin Fan, Dimin Niu, Meng Li, Zhiyong Li, Zongwei Wang, Hongzhong Zheng, Yimao Cai, Yuan Xie
2025 J jnl
MemTunnel: A CXL-Based Rack-Scale Host Memory Pooling Architecture for Cloud Service.
IEEE Trans. Parallel Distributed Syst.
Tianchan Guan, Yijin Guan, Zhaoyang Du, Jiacheng Ma, Boyu Tian, Zhao Wang, Teng Ma, Zheng Liu, Yang Kong, Yuan Xie, Mingyu Gao, Guangyu Sun, Hongzhong Zheng, Dimin Niu
2025 J jnl
SAFE: A Scalable Homomorphic Encryption Accelerator for Vertical Federated Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhaohui Chen, Zhen Gu, Yanheng Lu, Xuanle Ren, Ruiguang Zhong, Wen-jie Lu, Jiansong Zhang, Yichi Zhang, Hanghang Wu, Xiaofu Zheng, Heng Liu, Tingqiang Chu, Cheng Hong, Changzheng Wei, Dimin Niu, Yuan Xie
2025 A* conf
Unicorn: Unified Neural Image Compression with One Number Reconstruction.
ACM Multimedia
Qi Zheng, Haozhi Wang, Zihao Liu, Jiaming Liu, Zhijian Hao, Bu Chen, Min Li, Rui Wan, Peiye Liu, Yanheng Lu, Dimin Niu, Jinjia Zhou, Minge Jing, Yibo Fan
2024 — conf
HydraRPC: RPC in the CXL Era.
USENIX ATC
Teng Ma, Zheng Liu, Chengkun Wei, Jialiang Huang, Youwei Zhuo, Haoyu Li, Ning Zhang, Yijin Guan, Dimin Niu, Mingxing Zhang, Tao Ma
2024 — conf
Salus: A Practical Trusted Execution Environment for CPU-FPGA Heterogeneous Cloud Platforms.
ASPLOS (4)
Yu Zou, Yiran Li, Sheng Wang, Le Su, Zhen Gu, Yanheng Lu, Yijin Guan, Dimin Niu, Mingyu Gao, Yuan Xie, Feifei Li
2024 J jnl
Unicorn: Unified Neural Image Compression with One Number Reconstruction.
CoRR
Qi Zheng, Haozhi Wang, Zihao Liu, Jiaming Liu, Peiye Liu, Zhijian Hao, Yanheng Lu, Dimin Niu, Jinjia Zhou, Ming-e Jing, Yibo Fan
2024 A* conf
Zero-Shot Structure-Preserving Diffusion Model for High Dynamic Range Tone Mapping.
CVPR
Ruoxi Zhu, Shusong Xu, Peiye Liu, Sicheng Li, Yanheng Lu, Dimin Niu, Zihao Liu, Zihao Meng, Zhiyong Li, Xinhua Chen, Yibo Fan
2023 J jnl
Accelerating Distributed GNN Training by Codes.
IEEE Trans. Parallel Distributed Syst.
Yanhong Wang, Tianchan Guan, Dimin Niu, Qiaosha Zou, Hongzhong Zheng, Chuanjin Richard Shi, Yuan Xie
2023 A* conf
CHAM: A Customized Homomorphic Encryption Accelerator for Fast Matrix-Vector Product.
DAC
Xuanle Ren, Zhaohui Chen, Zhen Gu, Yanheng Lu, Ruiguang Zhong, Wen-jie Lu, Jiansong Zhang, Yichi Zhang, Hanghang Wu, Xiaofu Zheng, Heng Liu, Tingqiang Chu, Cheng Hong, Changzheng Wei, Dimin Niu, Yuan Xie
2023 J jnl
MNSIM 2.0: A Behavior-Level Modeling Tool for Processing-In-Memory Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhenhua Zhu, Hanbo Sun, Tongxin Xie, Yu Zhu, Guohao Dai, Lixue Xia, Dimin Niu, Xiaoming Chen, Xiaobo Sharon Hu, Yu Cao, Yuan Xie, Huazhong Yang, Yu Wang
2023 J jnl
MPU: Memory-centric SIMT Processor via In-DRAM Near-bank Computing.
ACM Trans. Archit. Code Optim.
Xinfeng Xie, Peng Gu, Yufei Ding, Dimin Niu, Hongzhong Zheng, Yuan Xie
2023 A* conf
NMExplorer: An Efficient Exploration Framework for DIMM-based Near-Memory Tensor Reduction.
DAC
Cong Li, Zhe Zhou, Xingchen Li, Guangyu Sun, Dimin Niu
2023 — conf
Spada: Accelerating Sparse Matrix Multiplication with Adaptive Dataflow.
ASPLOS (2)
Zhiyao Li, Jiaxiang Li, Taijie Chen, Dimin Niu, Hongzhong Zheng, Yuan Xie, Mingyu Gao
2023 A* conf
TT-GNN: Efficient On-Chip Graph Neural Network Training via Embedding Reformation and Hardware Optimization.
MICRO
Zheng Qu, Dimin Niu, Shuangchen Li, Hongzhong Zheng, Yuan Xie
2022 — conf
184QPS/W 64Mb/mm
ISSCC
Dimin Niu, Shuangchen Li, Yuhao Wang, Wei Han, Zhe Zhang, Yijin Guan, Tianchan Guan, Fei Sun, Fei Xue, Lide Duan, Yuanwei Fang, Hongzhong Zheng, Xiping Jiang, Song Wang, Fengguo Zuo, Yubing Wang, Bing Yu, Qiwei Ren, Yuan Xie
2022 J jnl
Accelerating CPU-Based Sparse General Matrix Multiplication With Binary Row Merging.
IEEE Access
Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Hongzhong Zheng, Yuan Xie
2022 J jnl
Accelerating CPU-based Sparse General Matrix Multiplication with Binary Row Merging.
CoRR
Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Hongzhong Zheng, Yuan Xie
2022 — conf
COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning.
ISSCC
Haozhe Zhu, Bo Jiao, Jinshan Zhang, Xinru Jia, Yunzhengmao Wang, Tianchan Guan, Shengcheng Wang, Dimin Niu, Hongzhong Zheng, Chixiao Chen, Mingyu Wang, Lihua Zhang, Xiaoyang Zeng, Qi Liu, Yuan Xie, Ming Liu
2022 A* conf
Enabling High-Quality Uncertainty Quantification in a PIM Designed for Bayesian Neural Network.
HPCA
Xingchen Li, Bingzhe Wu, Guangyu Sun, Zhe Zhang, Zhihang Yuan, Runsheng Wang, Ru Huang, Dimin Niu, Hongzhong Zheng, Zhichao Lu, Liang Zhao, Meng-Fan Marvin Chang, Tianchan Guan, Xin Si
2022 J jnl
Flatfish: A Reinforcement Learning Approach for Application-Aware Address Mapping.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xingchen Li, Zhihang Yuan, Yijin Guan, Guangyu Sun, Tao Zhang, Rongshan Wei, Dimin Niu
2022 A* conf
Hyperscale FPGA-as-a-service architecture for large-scale distributed graph neural network.
ISCA
Shuangchen Li, Dimin Niu, Yuhao Wang, Wei Han, Zhe Zhang, Tianchan Guan, Yijin Guan, Heng Liu, Linyong Huang, Zhaoyang Du, Fei Xue, Yuanwei Fang, Hongzhong Zheng, Yuan Xie
2022 J jnl
OpSparse: A Highly Optimized Framework for Sparse General Matrix Multiplication on GPUs.
IEEE Access
Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Linyong Huang, Hongzhong Zheng, Yuan Xie
2022 J jnl
OpSparse: a Highly Optimized Framework for Sparse General Matrix Multiplication on GPUs.
CoRR
Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Linyong Huang, Hongzhong Zheng, Yuan Xie
2022 J jnl
Practical Near-Data-Processing Architecture for Large-Scale Distributed Graph Neural Network.
IEEE Access
Linyong Huang, Zhe Zhang, Shuangchen Li, Dimin Niu, Yijin Guan, Hongzhong Zheng, Yuan Xie
2022 B conf
Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio.
ICPADS
Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Nianxiong Tan, Xiaopeng Yu, Hongzhong Zheng, Jianyi Meng, Xiaolang Yan, Yuan Xie
2022 J jnl
Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio.
CoRR
Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Nianxiong Tan, Xiaopeng Yu, Hongzhong Zheng, Jianyi Meng, Xiaolang Yan, Yuan Xie
2021 J jnl
Area Efficient Pattern Representation of Binary Neural Networks on RRAM.
J. Comput. Sci. Technol.
Feng Wang, Guojie Luo, Guang-Yu Sun, Yuhao Wang, Dimin Niu, Hongzhong Zheng
2021 J jnl
DLUX: A LUT-Based Near-Bank Accelerator for Data Center Deep Learning Training Workloads.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Peng Gu, Xinfeng Xie, Shuangchen Li, Dimin Niu, Hongzhong Zheng, Krishna T. Malladi, Yuan Xie
2021 J jnl
MPU: Towards Bandwidth-abundant SIMT Processor via Near-bank Computing.
CoRR
Xinfeng Xie, Peng Gu, Yufei Ding, Dimin Niu, Hongzhong Zheng, Yuan Xie
2021 J jnl
STAR: Synthesis of Stateful Logic in RRAM Targeting High Area Utilization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Feng Wang, Guojie Luo, Guangyu Sun, Jiaxi Zhang, Jinfeng Kang, Yuhao Wang, Dimin Niu, Hongzhong Zheng
2020 — conf
GNN-PIM: A Processing-in-Memory Architecture for Graph Neural Networks.
ACA
Zhao Wang, Yijin Guan, Guangyu Sun, Dimin Niu, Yuhao Wang, Hongzhong Zheng, Yinhe Han
2020 — conf
MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems.
ACM Great Lakes Symposium on VLSI
Zhenhua Zhu, Hanbo Sun, Kaizhong Qiu, Lixue Xia, Gokul Krishnan, Guohao Dai, Dimin Niu, Xiaoming Chen, Xiaobo Sharon Hu, Yu Cao, Yuan Xie, Yu Wang, Huazhong Yang
2020 A* conf
iPIM: Programmable In-Memory Image Processing Accelerator Using Near-Bank Architecture.
ISCA
Peng Gu, Xinfeng Xie, Yufei Ding, Guoyang Chen, Weifeng Zhang, Dimin Niu, Yuan Xie
2019 A* conf
GraphQ: Scalable PIM-Based Graph Processing.
MICRO
Youwei Zhuo, Chao Wang, Mingxing Zhang, Rui Wang, Dimin Niu, Yanzhi Wang, Xuehai Qian
2018 — conf
Performance Impact of Emerging Memory Technologies on Big Data Applications: A Latency-Programmable System Emulation Approach.
ACM Great Lakes Symposium on VLSI
Mu-Tien Chang, I. Stephen Choi, Dimin Niu, Hongzhong Zheng
2018 A* conf
SCOPE: A Stochastic Computing Engine for DRAM-Based In-Situ Accelerator.
MICRO
Shuangchen Li, Alvin Oliver Glova, Xing Hu, Peng Gu, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Yuan Xie
2017 J jnl
DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric.
IEEE Micro
Mingyu Gao, Christina Delimitrou, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Christos Kozyrakis
2017 A* conf
DRISA: a DRAM-based reconfigurable in-situ accelerator.
MICRO
Shuangchen Li, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Yuan Xie
2017 — conf
FlashStorageSim: Performance Modeling for SSD Architectures.
NAS
Krishna T. Malladi, Mu-Tien Chang, Dimin Niu, Hongzhong Zheng
2016 A* conf
DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric.
ISCA
Mingyu Gao, Christina Delimitrou, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Christos Kozyrakis
2015 J jnl
Impact of Cell Failure on Reliable Cross-Point Resistive Memory Design.
ACM Trans. Design Autom. Electr. Syst.
Cong Xu, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie
2015 J jnl
Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach.
IEEE Trans. Multi Scale Comput. Syst.
Cong Xu, Yang Zheng, Dimin Niu, Xiaochun Zhu, Seung-Hyuk Kang, Yuan Xie
2015 A* conf
Overcoming the challenges of crossbar resistive memory architectures.
HPCA
Cong Xu, Dimin Niu, Naveen Muralimanohar, Rajeev Balasubramonian, Tao Zhang, Shimeng Yu, Yuan Xie
2014 — conf
3DLAT: TSV-based 3D ICs crosstalk minimization utilizing Less Adjacent Transition code.
ASP-DAC
Qiaosha Zou, Dimin Niu, Yan Cao, Yuan Xie
2014 A conf
Architecting 3D vertical resistive memory for next-generation storage systems.
ICCAD
Cong Xu, Pai-Yu Chen, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie
2014 — conf
Modeling and design analysis of 3D vertical resistive memory - A low cost cross-point architecture.
ASP-DAC
Cong Xu, Dimin Niu, Shimeng Yu, Yuan Xie
2014 — conf
Reliability-aware cross-point resistive memory design.
ACM Great Lakes Symposium on VLSI
Cong Xu, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie
2014 A conf
SBAC: a statistics based cache bypassing method for asymmetric-access caches.
ISLPED
Chao Zhang, Guangyu Sun, Peng Li, Tao Wang, Dimin Niu, Yiran Chen
2013 A conf
Design of cross-point metal-oxide ReRAM emphasizing reliability and cost.
ICCAD
Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie
2013 C conf
Low power multi-level-cell resistive memory design with incomplete data mapping.
ICCD
Dimin Niu, Qiaosha Zou, Cong Xu, Yuan Xie
2013 A* conf
Understanding the trade-offs in multi-level cell ReRAM memory design.
DAC
Cong Xu, Dimin Niu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie
2012 A conf
Design trade-offs for high density cross-point resistive memory.
ISLPED
Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie
2012 — conf
Low power memristor-based ReRAM design with Error Correcting Code.
ASP-DAC
Dimin Niu, Yang Xiao, Yuan Xie
2012 — ch.
Low-Power Design of Emerging Memory Technologies.
Handbook of Energy-Aware and Green Computing
Yiran Chen, Hai Li, Yuan Xie, Dimin Niu
2011 — conf
A frequent-value based PRAM memory architecture.
ASP-DAC
Guangyu Sun, Dimin Niu, Jin Ouyang, Yuan Xie
2011 A conf
Device-architecture co-optimization of STT-RAM based memory for low power embedded systems.
ICCAD
Cong Xu, Dimin Niu, Xiaochun Zhu, Seung-Hyuk Kang, Matt Nowak, Yuan Xie
2011 C conf
Energy-efficient multi-level cell phase-change memory system with data encoding.
ICCD
Jue Wang, Xiangyu Dong, Guangyu Sun, Dimin Niu, Yuan Xie
2011 A conf
F
ICS
Jin Ouyang, Chuan Yang, Dimin Niu, Yuan Xie, Zhiwen Liu
2010 A* conf
A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement.
HPCA
Guangyu Sun, Yongsoo Joo, Yibo Chen, Dimin Niu, Yuan Xie, Yiran Chen, Hai Li
2010 A conf
Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis.
ICCAD
Yibo Chen, Dimin Niu, Yuan Xie, Krishnendu Chakrabarty
2010 — conf
Energy and performance driven circuit design for emerging phase-change memory.
ASP-DAC
Dimin Niu, Yibo Chen, Xiangyu Dong, Yuan Xie
2010 A conf
Energy- and endurance-aware design of phase change memory caches.
DATE
Yongsoo Joo, Dimin Niu, Xiangyu Dong, Guangyu Sun, Naehyuck Chang, Yuan Xie
2010 A* conf
Impact of process variations on emerging memristor.
DAC
Dimin Niu, Yiran Chen, Cong Xu, Yuan Xie
2010 A conf
Low-power dual-element memristor based memory design.
ISLPED
Dimin Niu, Yiran Chen, Yuan Xie